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Circuit design and technological limitations of silicon RFICs for wireless applications

Hitko, Donald A. (Donald Anthony)
Fonte: Massachusetts Institute of Technology Publicador: Massachusetts Institute of Technology
Tipo: Tese de Doutorado Formato: 206 p.; 21553012 bytes; 21552769 bytes; application/pdf; application/pdf
ENG
Relevância na Pesquisa
36.15%
Semiconductor technologies have been a key to the growth in wireless communication over the past decade, bringing added convenience and accessibility through advantages in cost, size, and power dissipation. A better understanding of how an IC technology affects critical RF signal chain components will greatly aid the design of wireless systems and the development of process technologies for the increasingly complex applications that lie on the horizon. Many of the evolving applications will embody the concept of adaptive performance to extract the maximum capability from the RF link in terms of bandwidth, dynamic range, and power consumption-further engaging the interplay of circuits and devices is this design space and making it even more difficult to discern a clear guide upon which to base technology decisions. Rooted in these observations, this research focuses on two key themes: 1) devising methods of implementing RF circuits which allow the performance to be dynamically tuned to match real-time conditions in a power-efficient manner, and 2) refining approaches for thinking about the optimization of RF circuits at the device level. Working toward a 5.8 GHz receiver consistent with 1 GBit/s operation, signal path topologies and adjustable biasing circuits are developed for low-noise amplifiers (LNAs) and voltage-controlled oscillators (VCOs) to provide a facility by which power can be conserved when the demand for sensitivity is low. As an integral component in this effort...

Double layer capacitors : automotive applications and modeling

New, David Allen, 1976-
Fonte: Massachusetts Institute of Technology Publicador: Massachusetts Institute of Technology
Tipo: Tese de Doutorado Formato: 227 p.; 15027449 bytes; 15056891 bytes; application/pdf; application/pdf
EN_US
Relevância na Pesquisa
36.15%
This thesis documents the work on the modeling of double layer capacitors (DLCs) and the validation of the modeling procedure. Several experiments were conducted to subject the device under test to a variety of charging/discharging profile and temperatures in an effort to simulate the various conditions such a device might encounter in an automotive type application. High and low current charging profiles were performed for both charge/discharge and charge/hold/discharge type experiments. Low temperature ([approx.] -25 ⁰C), room temperature ([approx.] 21 ⁰C), and high temperature experiments ([approx.] 50 ⁰C) were performed for the investigation of temperature effects on these devices. The derived DLC model was used in PSpice® and Matlab® simulations to determine how accurately the model could predict the performance of the device. The nonlinear characteristics of the device were also investigated and the nonlinear modeling information presented as an addition to the basic DLC model. Device variation was explored for a small sample of these devices in an effort to gain insight on the range of tolerances for modern devices. This work also presents an extensive look into the variety of electrochemical capacitor devices under investigation and in use today. An explanation of these devices and their distributed resistances and capacitance is included. This thesis gives a detailed look into the experimental setups and testing procedures used to test the devices...

Copper wafer bonding in three-dimensional integration

Chen, Kuan-Neng, 1974-
Fonte: Massachusetts Institute of Technology Publicador: Massachusetts Institute of Technology
Tipo: Tese de Doutorado Formato: 176 p.; 7404641 bytes; 7426947 bytes; application/pdf; application/pdf
ENG
Relevância na Pesquisa
36.15%
Three-dimensional (3D) integration, in which multiple layers of devices are stacked with high density of interconnects between the layers, offers solutions for problems when the critical dimensions in integrated circuits keep shrinking. Copper wafer bonding has been considered as a strong candidate for fabrication of three-dimensional integrated circuits (3-D IC). This thesis work involves fundamental studies of copper wafer bonding and bonding performance of bonded interconnects. Copper bonded wafers exhibit good bonding qualities and present no original bonding interfaces when the bonding process occurs at 400⁰C/4000 mbar for 30 min, followed by nitrogen anneal at 400⁰C for 30 min. Oxide distribution in the bonded layer is uniform and sparse. Evolution of microstructure morphologies and grain orientations of copper bonded wafers during bonding and annealing were studied. The bonded layer reaches steady state after post-bonding anneal. The microstructure morphologies and bond strengths of copper bonded wafers under different bonding conditions were investigated.A map summarizing these results provides a useful reference on process conditions suitable for three-dimensional integration based on copper wafer bonding. Similar microstructure morphology of copper bonded interconnects was observed to that of copper bonded wafers. Specific contact resistances of bonded interconnects of approximately 10⁻⁸ [ohms]-cm² were measured by using a novel test structure which can eliminate the errors from misalignment during bonding. The bonding qualities of different interconnect sizes and densities have been investigated. In addition to increasing the bonding temperature and duration...

Deeply scaled CMOS for RF power applications

Scholvin, Jörg, 1976-
Fonte: Massachusetts Institute of Technology Publicador: Massachusetts Institute of Technology
Tipo: Tese de Doutorado Formato: 140 p.
ENG
Relevância na Pesquisa
36.15%
The microelectronics industry is striving to reduce the cost, complexity, and form factor of wireless systems through single-chip integration of analog, RF and digital functions. Driven by the requirements of the digital system components, the 90 nm and 65 nm technology nodes are currently emerging as platforms for highly integrated systems. Achieving such integration while minimizing the cost of adding specialized RF modules places high demands on the base CMOS technology. In this regard, the integration of the power amplifier (PA) function becomes an increasing challenge as technology geometries and supply voltages scale down. Gate length (Lg) scaling yields improved frequency response, promising higher power-added efficiency (PAE), a key RF PA consideration. This benefit comes at the cost of a lower drain voltage, which demands a higher output current and thus wider devices in order to produce a given output power level (Po,,). In this work, we have investigated the potential of deeply scaled CMOS for RF power applications, from 0.25 um down to 65 nm. We demonstrate the frequency and power limitations that the different CMOS technologies face, and describe the physical mechanisms that give rise to these limitations.; (cont.) We find that layout considerations...

Electric field engineering in GaN high electron mobility transistors

Zhao, Xu, S.M. Massachusetts Institute of Technology
Fonte: Massachusetts Institute of Technology Publicador: Massachusetts Institute of Technology
Tipo: Tese de Doutorado Formato: 70 leaves
ENG
Relevância na Pesquisa
36.37%
In the last few years, AlGaN/GaN high electron mobility transistors (HEMTs) have become the top choice for power amplification at frequencies up to 20 GHz. Great interest currently exists in industry and academia to increase the frequency to mm-wave frequencies. The goal of this thesis has been to identify new solutions to some of the main challenges to increase this frequency performance even further. Electron velocity is a critical parameter affecting the transistor performance. In standard GaN transistors, the extremely high electric fields present in the channel of the device reduce the average electron velocity well below the peak electron velocity, resulting in low cutoff frequencies. In this thesis, we introduced a partial recess in the drain access region of the transistor to engineer the electric field along the channel of the device without introducing parasitic capacitances. By reducing the peak electric field, the average electron velocity is increased by 50%. This new technology has the potential to improve not only the cutoff frequencies, but also the breakdown voltage of GaN transistors. To successfully engineer the electric field in GaN devices, an accurate, reliable and low damage etching technology is needed. However none of the traditional GaN dry etching technologies meets these requirements. This lack of suitable technology has motivated us to develop a new atomic layer etching technique of AlGaN/GaN structures. This technology has been shown to be a self limited process with very high reliability and low damage...