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Modular and generic WCET static analysis with LLVM framework; Análise estática, genérica e modular de WCET utilizando a infra-estrutura de compilação do LLVM

Fachini, Guilherme James de Angelis
Fonte: Universidade Federal do Rio Grande do Sul Publicador: Universidade Federal do Rio Grande do Sul
Tipo: Trabalho de Conclusão de Curso Formato: application/pdf
ENG
Relevância na Pesquisa
46.14%
O cálculo do tempo do pior-caso de execução, do inglês Worst Case Execution Time (WCET) é um desafio na área de verificação de software para sistemas de tempo real. Essa análise faz parte do trabalho de escalonamento de tarefas de processos em sistemas multi-cores. A complexidade de prever esse tempo aumenta de acordo com a complexidade do hardware do sistema a ser analisado e seus componentes, já que muitas partes de uma plataforma, como pipelines e memória cache inserem variantes no tempo de execução difíceis de prever e analisar. Existem vários métodos com diferentes abordagens para se calcular o tempo de execução de um programa. Eles são principalmente baseados em análises estáticas e dinâmicas, de forma que a estática utiliza um modelo de hardware e analisa o código, enquanto a dinâmica necessita de algum simulador ou de uma plataforma real para realizar as medidas de tempo. Esse trabalho apresenta um modelo de análise estática para prever o tempo do piorcaso de execução de códigos para sistemas embarcados de tempo real. Além disso, executa, para fins de comparação, uma análise dinâmica baseado na execução dos códigos de teste em um simulador. O modelo de análise estática é desenvolvido baseado em um assembly gerado pela infra-estrutura de compilação do LLVM...

Uma Abordagem de escalonamento heterogêneo preemptivo e não preemptivo para sistemas de tempo real com garantia em multiprocessadores

Starke, Renan Augusto
Fonte: Florianópolis, SC Publicador: Florianópolis, SC
Tipo: Dissertação de Mestrado Formato: 198 p.| il., grafs., tabs.
POR
Relevância na Pesquisa
45.98%
Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Engenharia de Automação e Sistemas; Sistemas de tempo real são sistemas onde o correto funcionamento não depende somente da resposta lógica correta, mas também do tempo no qual ela foi dada. Igualmente do ponto de vista lógico, a viabilidade temporal da aplicação deve ser determinada através de técnicas, como por exemplo análise do tempo de reposta. Este tipo de aplicação está cada vez mais presente atualmente e a demanda de processamento é tamanha que necessita-se de processadores com múltiplos núcleos complexos. É perceptível que o desenvolvimento dos multiprocessadores está muito mais avançado em relação às técnicas de análise de tais sistemas e, portanto, é evidente a necessidade de pesquisa com objetivo de promover maior confiabilidade e redução de superdimensionamentos. O objetivo deste trabalho é promover uma solução de escalonamento que considere a escalonabilidade em conjunto com a analisabilidade do código da aplicação. Atualmente, a pesquisa de sistemas de tempo real trata o problema do escalonamento isolado do problema de obtenção do parâmetro do tempo de computação da tarefas (WCET --Worst Case Execution Time). Dependendo da arquitetura do processador...

A holistic approach towards flexible distributed systems; Flexibilização em sistemas distribuídos: uma perspectiva holística

Calha, Mário João Barata
Fonte: Universidade de Aveiro Publicador: Universidade de Aveiro
Tipo: Tese de Doutorado
ENG
Relevância na Pesquisa
45.88%
Em sistemas distribuídos o paradigma utilizado para interacção entre tarefas é a troca de mensagens. Foram propostas várias abordagens que permitem a especificação do fluxo de dados entre tarefas, mas para sistemas de temporeal é necessário uma definição mais rigorosa destes fluxos de dados. Nomeadamente, tem de ser possível a especificação dos parâmetros das tarefas e das mensagens, e a derivação dos parâmetros não especificados. Uma tal abordagem poderia permitir o escalonamento e despacho automático de tarefas e de mensagens, ou pelo menos, poderia reduzir o número de iterações durante o desenho do sistema. Os fluxos de dados constituem uma abordagem possível ao escalonamento e despacho holístico em sistemas distribuídos de tempo-real, onde são realizadas diferentes tipos de análises que correlacionam os vários parâmetros. Os resultados podem ser utilizados para definir o nível de memória de suporte que é necessário em cada nodo do sistema distribuído. Em sistemas distribuídos baseados em FTT, é possível implementar um escalonamento holístico centralizado, no qual se consideram as interdependências entre tarefas produtoras/consumidoras e mensagens. O conjunto de restrições que garante a realização do sistema pode ser derivado dos parâmetros das tarefas e das mensagens...

Fixed priority analysis for real-time multiprocessors; Análise de prioridade fixa em multiprocessadores de tempo-real

Bastos, João Pedro Nogueira
Fonte: Universidade de Aveiro Publicador: Universidade de Aveiro
Tipo: Dissertação de Mestrado
ENG
Relevância na Pesquisa
45.91%
MultiProcessor Systems-on-chip (MPSoCs) are versatile and powerful platforms designed to t the needs of modern embedded applications, such as radios and audio/video decoders. However, in a MPSoC running several applications simultaneously, resources must be shared while the timing constraints of each application must be met. Embedded streaming applications mapped on a MPSoC, are often modeled using data ow graphs. Data ow graphs have the expressivity and analytical properties to naturally describe concurrent digital signal processing applications. Many scheduling strategies have been analyzed using data ow models of applications, such as Time Division Multiplexing (TDM) and Non-preemptive Non-blocking Round Robin (NPNBRR). However, few approaches have focused on a preemptive Fixed Priority (FP) scheduling scheme. Fixed Priority scheduling is a simple and often used scheduling scheme. It is easy to implement in any platform and it is quite predictable under overload conditions. This dissertation studies the temporal analysis of a set of data ow modeled applications mapped on the same resources and scheduled with a xed priority scheme. Our objective is to improve the existing analysis for Single Rate Data ow (SRDF) graphs and develop the necessary concepts and techniques to extend it for applications modeled with state-of-art data ow avor...

Modeling assembly program with constraints. A contribution to WCET problem

Kafle, Bishoksan
Fonte: Faculdade de Ciências e Tecnologia Publicador: Faculdade de Ciências e Tecnologia
Tipo: Dissertação de Mestrado
Publicado em //2012 ENG
Relevância na Pesquisa
86%
Dissertação para obtenção do Grau de Mestre em Lógica Computacional; Model checking with program slicing has been successfully applied to compute Worst Case Execution Time (WCET) of a program running in a given hardware. This method lacks path feasibility analysis and suffers from the following problems: The model checker (MC) explores exponential number of program paths irrespective of their feasibility. This limits the scalability of this method to multiple path programs. And the witness trace returned by the MC corresponding to WCET may not be feasible (executable). This may result in a solution which is not tight i.e., it overestimates the actual WCET. This thesis complements the above method with path feasibility analysis and addresses these problems. To achieve this: we first validate the witness trace returned by the MC and generate test data if it is executable. For this we generate constraints over a trace and solve a constraint satisfaction problem. Experiment shows that 33% of these traces (obtained while computing WCET on standard WCET benchmark programs) are infeasible. Second, we use constraint solving technique to compute approximate WCET solely based on the program (without taking into account the hardware characteristics)...

An On-Time Power-Aware Scheduling Scheme for Medical Sensor SoC-Based WBAN Systems

Hwang, Tae-Ho; Kim, Dong-Sun; Kim, Jung-Guk
Fonte: Molecular Diversity Preservation International (MDPI) Publicador: Molecular Diversity Preservation International (MDPI)
Tipo: Artigo de Revista Científica
Publicado em 27/12/2012 EN
Relevância na Pesquisa
55.74%
The focus of many leading technologies in the field of medical sensor systems is on low power consumption and robust data transmission. For example, the implantable cardioverter-defibrillator (ICD), which is used to maintain the heart in a healthy state, requires a reliable wireless communication scheme with an extremely low duty-cycle, high bit rate, and energy-efficient media access protocols. Because such devices must be sustained for over 5 years without access to battery replacement, they must be designed to have extremely low power consumption in sleep mode. Here, an on-time, energy-efficient scheduling scheme is proposed that performs power adjustments to minimize the sleep-mode current. The novelty of this scheduler is that it increases the determinacy of power adjustment and the predictability of scheduling by employing non-pre-emptible dual priority scheduling. This predictable scheduling also guarantees the punctuality of important periodic tasks based on their serialization, by using their worst case execution time) and the power consumption optimization. The scheduler was embedded into a system on chip (SoC) developed to support the wireless body area network—a wakeup-radio and wakeup-timer for implantable medical devices. This scheduling system is validated by the experimental results of its performance when used with life-time extensions of ICD devices.

Combining Instruction Prefetching with Partial Cache Locking to Improve WCET in Real-Time Systems

Ni, Fan; Long, Xiang; Wan, Han; Gao, Xiaopeng
Fonte: Public Library of Science Publicador: Public Library of Science
Tipo: Artigo de Revista Científica
Publicado em 26/12/2013 EN
Relevância na Pesquisa
56.05%
Caches play an important role in embedded systems to bridge the performance gap between fast processor and slow memory. And prefetching mechanisms are proposed to further improve the cache performance. While in real-time systems, the application of caches complicates the Worst-Case Execution Time (WCET) analysis due to its unpredictable behavior. Modern embedded processors often equip locking mechanism to improve timing predictability of the instruction cache. However, locking the whole cache may degrade the cache performance and increase the WCET of the real-time application. In this paper, we proposed an instruction-prefetching combined partial cache locking mechanism, which combines an instruction prefetching mechanism (termed as BBIP) with partial cache locking to improve the WCET estimates of real-time applications. BBIP is an instruction prefetching mechanism we have already proposed to improve the worst-case cache performance and in turn the worst-case execution time. The estimations on typical real-time applications show that the partial cache locking mechanism shows remarkable WCET improvement over static analysis and full cache locking.

Automatic Time-Bound Analysis for High-Level Languages

Gomez, Gustavo
Fonte: [Bloomington, Ind.] : Indiana University Publicador: [Bloomington, Ind.] : Indiana University
Tipo: Doctoral Dissertation
EN
Relevância na Pesquisa
75.89%
Thesis (PhD) - Indiana University, Computer Sciences, 2006; Analysis of program running time is important for reactive systems, interactive environments, compiler optimizations, performance evaluation, and many other computer applications. Automatic and efficient prediction of accurate time bounds is particularly important, and being able to do so for high-level languages is particularly desirable. This dissertation presents a general approach for automatic and accurate time-bound analysis for high-level languages, combining methods and techniques studied in theory, languages, and systems. The approach consists of transformations for building time-bound functions in the presence of partially known input structures, symbolic evaluation of the time-bound function based on input parameters, optimizations to make the analysis efficient as well as accurate, and measurements of primitive parameters, all at the source-language level. We describe analysis and transformation algorithms and explain how they work. We have implemented this approach and performed a large number of experiments analyzing Scheme programs. The measured worst-case times are closely bounded by the calculated bounds. We describe our prototype system, ALPA, as well as the analysis and measurement results.

Real-time operating system support for multicore applications

Gracioli, Giovani
Fonte: Universidade Federal de Santa Catarina Publicador: Universidade Federal de Santa Catarina
Tipo: Tese de Doutorado Formato: 359 p.| il., grafs., tabs.
ENG
Relevância na Pesquisa
45.91%
Tese (doutorado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Engenharia de Automação e Sistemas, Florianópolis, 2014; Plataformas multiprocessadas atuais possuem diversos níveis da memória cache entre o processador e a memória principal para esconder a latência da hierarquia de memória. O principal objetivo da hierarquia de memória é melhorar o tempo médio de execução, ao custo da previsibilidade. O uso não controlado da hierarquia da cache pelas tarefas de tempo real impacta a estimativa dos seus piores tempos de execução, especialmente quando as tarefas de tempo real acessam os níveis da cache compartilhados. Tal acesso causa uma disputa pelas linhas da cache compartilhadas e aumenta o tempo de execução das aplicações. Além disso, essa disputa na cache compartilhada pode causar a perda de prazos, o que é intolerável em sistemas de tempo real críticos. O particionamento da memória cache compartilhada é uma técnica bastante utilizada em sistemas de tempo real multiprocessados para isolar as tarefas e melhorar a previsibilidade do sistema. Atualmente, os estudos que avaliam o particionamento da memória cache em multiprocessadores carecem de dois pontos fundamentais. Primeiro...

Timing analysis: from predictions to certificates

Gaspar, Nuno Miguel Pires
Fonte: Universidade da Beira Interior Publicador: Universidade da Beira Interior
Tipo: Dissertação de Mestrado
Publicado em //2010 ENG
Relevância na Pesquisa
75.85%
In real-time systems timing properties must be satisfied in order to guarantee that deadlines will be met. In this context, the calculation of theworst-case execution time(WCET) is of paramount importance for schedulability analysis. However, this problem can be difficult if the underlying architecture possesses features like caches and pipelines. This thesis presents all the necessary steps for the safe and preciseWCET calculation. We focus ourselves in the use of static analysis-based methods, and in the ARMarchitecture as target platform. Moreover, in order to ensure the correctness of our calculation to a program consumer, we produce a certificate (or proof ) whose validity entails compliance with the calculated WCET. This evidence permits to locally validate the calculated WCET, avoiding the need of a blind confidence on the producer.

Precise Schedulability Analysis for unfeasible to notify separately for comprehensive - EDF Scheduling of interrupted Hard Real-Time Tasks on the similar Multiprocessors

Singh, Jagbeer
Fonte: Universidade Cornell Publicador: Universidade Cornell
Tipo: Artigo de Revista Científica
Publicado em 10/01/2011
Relevância na Pesquisa
55.73%
In Real-time system, utilization based schedulability test is a common approach to determine whether or not tasks can be admitted without violating deadline requirements. The exact problem has previously been proven intractable even upon single processors; sufficient conditions are presented here for determining whether a given periodic task system will meet all deadlines if scheduled non-preemptively upon a multiprocessor platform using the earliest-deadline first scheduling algorithm. Many real-time scheduling algorithms have been developed recently to reduce affinity in the portable devices that use processors. Extensive power aware scheduling techniques have been published for energy reduction, but most of them have been focused solely on reducing the processor affinity. The non-preemptive scheduling of periodic task systems upon processing platforms comprised of several same processors is considered.; Comment: 9 pages,1 figure

Data dependent energy modelling for worst case energy consumption analysis

Pallister, James; Kerrison, Steve; Morse, Jeremy; Eder, Kerstin
Fonte: Universidade Cornell Publicador: Universidade Cornell
Tipo: Artigo de Revista Científica
Relevância na Pesquisa
65.99%
This paper examines the impact of operand values upon instruction level energy models of embedded processors, to explore whether the requirements for safe worst case energy consumption (WCEC) analysis can be met. WCEC is similar to worst case execution time (WCET) analysis, but seeks to determine whether a task can be completed within an energy budget rather than within a deadline. Existing energy models that underpin such analysis typically use energy measurements from random input data, providing average or otherwise unbounded estimates not necessarily suitable for worst case analysis. We examine energy consumption distributions of two benchmarks under a range of input data on two cache-less embedded architectures, AVR and XS1-L. We find that the worst case can be predicted with a distribution created from random data. We propose a model to obtain energy distributions for instruction sequences that can be composed, enabling WCEC analysis on program basic blocks. Data dependency between instructions is also examined, giving a case where dependencies create a bimodal energy distribution. The worst case energy prediction remains safe. We conclude that worst-case energy models based on a probabilistic approach are suitable for safe WCEC analysis.

How to Compute Worst-Case Execution Time by Optimization Modulo Theory and a Clever Encoding of Program Semantics

Henry, Julien; Asavoae, Mihail; Monniaux, David; Maïza, Claire
Fonte: Universidade Cornell Publicador: Universidade Cornell
Tipo: Artigo de Revista Científica
Publicado em 30/05/2014
Relevância na Pesquisa
85.98%
In systems with hard real-time constraints, it is necessary to compute upper bounds on the worst-case execution time (WCET) of programs; the closer the bound to the real WCET, the better. This is especially the case of synchronous reactive control loops with a fixed clock; the WCET of the loop body must not exceed the clock period. We compute the WCET (or at least a close upper bound thereof) as the solution of an optimization modulo theory problem that takes into account the semantics of the program, in contrast to other methods that compute the longest path whether or not it is feasible according to these semantics. Optimization modulo theory extends satisfiability modulo theory (SMT) to maximization problems. Immediate encodings of WCET problems into SMT yield formulas intractable for all current production-grade solvers; this is inherent to the DPLL(T) approach to SMT implemented in these solvers. By conjoining some appropriate "cuts" to these formulas, we considerably reduce the computation time of the SMT-solver. We experimented our approach on a variety of control programs, using the OTAWA analyzer both as baseline and as underlying microarchitectural analysis for our analysis, and show notable improvement on the WCET bound on a variety of benchmarks and control programs.; Comment: ACM SIGPLAN/SIGBED Conference on Languages...

Dynamic Priority Queue: An SDRAM Arbiter With Bounded Access Latencies for Tight WCET Calculation

Shah, Hardik; Raabe, Andreas; Knoll, Alois
Fonte: Universidade Cornell Publicador: Universidade Cornell
Tipo: Artigo de Revista Científica
Publicado em 05/07/2012
Relevância na Pesquisa
45.88%
This report introduces a shared resource arbitration scheme "DPQ - Dynamic Priority Queue" which provides bandwidth guarantees and low worst case latency to each master in an MPSoC. Being a non-trivial candidate for timing analysis, SDRAM has been chosen as a showcase, but the approach is valid for any shared resource arbitration. Due to its significant cost, data rate and physical size advantages, SDRAM is a potential candidate for cost sensitive, safety critical and space conserving systems. The variable access latency is a major drawback of SDRAM that induces largely over estimated Worst Case Execution Time (WCET) bounds of applications. In this report we present the DPQ together with an algorithm to predict the shared SDRAM's worst case latencies. We use the approach to calculate WCET bounds of six hardware tasks executing on an Altera Cyclone III FPGA with shared DDR2 memory. The results show that the DPQ is a fair arbitration scheme and produces low WCET bounds.

A survey of topological work at CEOL

Pajoohesh, Homeira; Schellekens, M. P.
Fonte: Universidade Cornell Publicador: Universidade Cornell
Tipo: Artigo de Revista Científica
Publicado em 31/12/2004
Relevância na Pesquisa
45.95%
We present an overview of ongoing work at the Centre for Efficiency-Oriented languages (CEOL), with a focus on topological aspects. CEOL researchers are engaged in designing a new Real-Time Language to improve software timing. The centre broadly focuses on bridging Semantics and Complexity and unites researchers with expertise in Semantics of Programming Languages, Real-Time Languages, Compiler Design and Graph Based Algorithms. CEOL aims to narrow the gap between Worst Case Execution Time analysis and Average Case Execution Time analysis for Real-Time languages and its longer term goal is the development of ACETT, an Average Case Execution Time Tool. This research work is of crucial interest to industry, given that real-time software is widely used in a variety of applications, such as chemical plants, satellite communications, the space industry, telephone exchanges, medical equipment, the motor industry, etc. Topological work at CEOL focuses on the exploration of quantitative Domains, semivaluations, partial metrics and their applications. We give an overview of prior results obtained at CEOL in this area and of current work on relating the notion of balance of algorithms to running time and of an exploration of semivaluations in relation to algorithmic running time.; Comment: 7 pages

Worst-case Throughput Analysis for Parametric Rate and Parametric Actor Execution Time Scenario-Aware Dataflow Graphs

Skelin, Mladen; Geilen, Marc; Catthoor, Francky; Hendseth, Sverre
Fonte: Universidade Cornell Publicador: Universidade Cornell
Tipo: Artigo de Revista Científica
Publicado em 31/03/2014
Relevância na Pesquisa
45.98%
Scenario-aware dataflow (SADF) is a prominent tool for modeling and analysis of dynamic embedded dataflow applications. In SADF the application is represented as a finite collection of synchronous dataflow (SDF) graphs, each of which represents one possible application behaviour or scenario. A finite state machine (FSM) specifies the possible orders of scenario occurrences. The SADF model renders the tightest possible performance guarantees, but is limited by its finiteness. This means that from a practical point of view, it can only handle dynamic dataflow applications that are characterized by a reasonably sized set of possible behaviours or scenarios. In this paper we remove this limitation for a class of SADF graphs by means of SADF model parametrization in terms of graph port rates and actor execution times. First, we formally define the semantics of the model relevant for throughput analysis based on (max,+) linear system theory and (max,+) automata. Second, by generalizing some of the existing results, we give the algorithms for worst-case throughput analysis of parametric rate and parametric actor execution time acyclic SADF graphs with a fully connected, possibly infinite state transition system. Third, we demonstrate our approach on a few realistic applications from digital signal processing (DSP) domain mapped onto an embedded multi-processor architecture.; Comment: In Proceedings SynCoP 2014...

Managing Varying Worst Case Execution Times on DVS Platforms

Berten, Vandy; Chang, Chi-Ju; Kuo, Tei-Wei
Fonte: Universidade Cornell Publicador: Universidade Cornell
Tipo: Artigo de Revista Científica
Publicado em 06/09/2008
Relevância na Pesquisa
76.11%
Energy efficient real-time task scheduling attracted a lot of attention in the past decade. Most of the time, deterministic execution lengths for tasks were considered, but this model fits less and less with the reality, especially with the increasing number of multimedia applications. It's why a lot of research is starting to consider stochastic models, where execution times are only known stochastically. However, authors consider that they have a pretty much precise knowledge about the properties of the system, especially regarding to the worst case execution time (or worst case execution cycles, WCEC). In this work, we try to relax this hypothesis, and assume that the WCEC can vary. We propose miscellaneous methods to react to such a situation, and give many simulation results attesting that with a small effort, we can provide very good results, allowing to keep a low deadline miss rate as well as an energy consumption similar to clairvoyant algorithms.

Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software

Wehmeyer, Lars; Marwedel, Peter
Fonte: Universidade Cornell Publicador: Universidade Cornell
Tipo: Artigo de Revista Científica
Publicado em 25/10/2007
Relevância na Pesquisa
55.75%
Safety-critical embedded systems having to meet real-time constraints are expected to be highly predictable in order to guarantee at design time that certain timing deadlines will always be met. This requirement usually prevents designers from utilizing caches due to their highly dynamic, thus hardly predictable behavior. The integration of scratchpad memories represents an alternative approach which allows the system to benefit from a performance gain comparable to that of caches while at the same time maintaining predictability. In this work, we compare the impact of scratchpad memories and caches on worst case execution time (WCET) analysis results. We show that caches, despite requiring complex techniques, can have a negative impact on the predicted WCET, while the estimated WCET for scratchpad memories scales with the achieved Performance gain at no extra analysis cost.; Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

On Systematic Testing for Execution-Time Analysis

Bundala, Daniel; Seshia, Sanjit A.
Fonte: Universidade Cornell Publicador: Universidade Cornell
Tipo: Artigo de Revista Científica
Publicado em 19/06/2015
Relevância na Pesquisa
66.05%
Given a program and a time deadline, does the program finish before the deadline when executed on a given platform? With the requirement to produce a test case when such a violation can occur, we refer to this problem as the worst-case execution-time testing (WCETT) problem. In this paper, we present an approach for solving the WCETT problem for loop-free programs by timing the execution of a program on a small number of carefully calculated inputs. We then create a sequence of integer linear programs the solutions of which encode the best timing model consistent with the measurements. By solving the programs we can find the worst-case input as well as estimate execution time of any other input. Our solution is more accurate than previous approaches and, unlikely previous work, by increasing the number of measurements we can produce WCETT bounds up to any desired accuracy. Timing of a program depends on the properties of the platform it executes on. We further show how our approach can be used to quantify the timing repeatability of the underlying platform.

Schedulability-driven scratchpad memory swapping for resource-constrained real-time embedded systems

De Francis, Michael
Fonte: Rochester Instituto de Tecnologia Publicador: Rochester Instituto de Tecnologia
Tipo: Tese de Doutorado
EN_US
Relevância na Pesquisa
66.08%
In resource-constrained real-time embedded systems, scratchpad memory (SPM) is utilized in place of cache to increase performance and enforce consistent behavior of both hard and soft real-time tasks via software-controlled SPM management techniques (SPMMTs). Real-time systems depend on time critical (hard) tasks to complete execution before their deadline times. Many real-time systems also depend on the execution of soft tasks that do not have to complete by hard deadlines. This thesis evaluates a new SPMMT that increases both worst-case task slack time (TST) and soft task processing capabilities, by combining two existing SPMMTs. The schedulability-driven ACETRB / WCETRB swapping (SDAWS) SPMMT of this thesis uses task schedulability characteristics to control the selection of either the average-case execution time reduction based (ACETRB) SPMMT or the worst-case execution time reduction based (WCETRB) SPMMT. While the literature contains examples of combined management techniques, until now there have been none that combine both WCETRB and ACETRB SPMMTs. The advantage of combining them is to achieve WCET reduction comparable to what can be achieved with the WCETRB SPMMT, while achieving significantly reduced ACET relative to the WCETRB SPMMT. Using a stripped-down RTOS and an SPMMT simulator implemented for this work...