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CMOS digital integrated circuit design faced to NBTI and other nanometric effects; Projeto de circuitos integrados digitais CMOS face ao NBTI e outros efeitos nanométricos

Dal Bem, Vinícius
Fonte: Universidade Federal do Rio Grande do Sul Publicador: Universidade Federal do Rio Grande do Sul
Tipo: Dissertação Formato: application/pdf
ENG
Relevância na Pesquisa
66.08%
Esta dissertação explora os desafios agravados pela miniaturização da tecnologia na fabricação e projeto de circuitos integrados digitais. Os efeitos físicos do regime nanométrico reduzem o rendimento da produção e encurtam a vida útil dos dispositivos, restringindo a utilidade dos padrões de projeto convencionais e ameaçando a evolução da tecnologia CMOS como um todo. Nesta dissertação é exposta uma consistente revisão bibliográfica dos principais efeitos físicos parasitas presentes no regime nanométrico. Como o NBTI tem recebido destaque na literatura relacionada à confiabilidade de circuitos, este efeito de envelhecimento recebe destaque também neste texto, sendo explorado mais detalhadamente. Diversas técnicas de avaliação de redução do NBTI são demonstradas, sendo apresentados, em cada um destes tópicos, trabalhos desenvolvidos no âmbito desta dissertação e seus resultados. O circuito proposto como técnica de avaliação de NBTI permite uso de simulações elétricas para análise de degradação de circuitos. A análise da influência do rearranjo da estrutura de transistores para reduzir a degradação quanto ao NBTI apresenta bons resultados e não impede o uso de outras técnicas combinadas.; This thesis explores the challenges worsened by the technology miniaturization in fabrication and design of digital integrated circuits. The physical effects of nanometric regime reduce the production yield and shorten the devices lifetime...

Automação do fluxo de projeto de circuitos integrados atraves do desenvolvimento de uma interface grafica parametrica implementada em TCL/TK; Integrated circuit design flow automation using a parametric graphical interface implemented using TCL/TK packages

Eduardo Henrique Tozetto
Fonte: Biblioteca Digital da Unicamp Publicador: Biblioteca Digital da Unicamp
Tipo: Dissertação de Mestrado Formato: application/pdf
Publicado em 31/07/2007 PT
Relevância na Pesquisa
76.13%
O contexto econômico competitivo em que as empresas que desenvolvem ferramentas para projeto de CIs estão inseridas dificulta o estabelecimento de padrões e plataformas de desenvolvimento comuns. Em geral, a necessidade de inúmeras ferramentas resulta em um ambiente de projeto fragmentado. Este trabalho apresenta uma ferramenta desenvolvida através da implementação de interfaces gráficas paramétricas em TCL/TK, que integra funções gerais, permitindo a rápida codificação de procedimentos e seu acesso através de elementos gráficos. A ferramenta desenvolvida serve para facilitar e otimizar as tarefas envolvidas no aprimoramento das técnicas de projeto de Circuitos ntegrados através da elaboração de métodos e scripts visando à automação de etapas do fluxo de projeto; The competitive environment in which the companies who develop software tools for the design of integrated circuits creates many barriers to the establishment of standards and common platforms. Usually the need for several software tools leads to a design environment which is fragmented and difficult to manage. This work presents the development of software tool, based on graphical parametric user interfaces in TCL/TK, which integrates many general functions and allows for a quick codification of procedures and its access through the graphics elements. The developed tool optimizes and facilitates the tasks employed in the improvement of the techniques used in integrated circuits design through the elaboration of methods and scripts dedicated to the automation of the design flow steps

Desenvolvimento de tecnologia de dispositivos chaves MEMS - MicroelectromechanicalSystems - para RF - Radio Frequencia - e novas topologias para circuitos integrados CMOS de RF em sub-sistemas de entrada de radio receptores; Development of MEMS switch device technology MEMS - MicroelectromechanicalSystems - for RF - radio frequency - and new topologies of RF CMOS integrated circuits for radio receivers input sub-systems

Andre Tavora de Albuquerque Silva
Fonte: Biblioteca Digital da Unicamp Publicador: Biblioteca Digital da Unicamp
Tipo: Tese de Doutorado Formato: application/pdf
Publicado em 29/02/2008 PT
Relevância na Pesquisa
66.28%
Este trabalho apresenta dois tópicos de pesquisa, o primeiro é referente ao projeto e desenvolvimento da tecnologia de fabricação de Chaves MEMS (Micro Electro Mechanical System) de RF e o segundo é o projeto de circuitos integrados. No que se refere a chaves MEMS, descreve-se o processo e a metodologia para projeto de Chaves MEMS paralela sobre linha de transmissão coplanar (CPW). A estrutura é composta de uma ponte metálica suspensa em ambos os lados por dois postes metálicos conectados ao plano de terra. As chaves são projetadas para uma baixa tensão de ativação (16 V) e com larga banda de operação em freqüência (400 MHz ? 4GHz) possibilitando seu uso na maioria dos padrões de sistemas de comunicação. Também é descrita a metodologia do projeto auxiliado por simulações eletromecânicas e eletromagnéticas e finalmente é apresentada a caracterização de 4 chaves construídas. Após extensa pesquisa na literatura técnico-científica, foi identificado que este é o primeiro trabalho no Brasil dedicado ao desenvolvimento de tecnologia de fabricação de chaves MEMS. Os projetos de circuitos integrados foram realizados em tecnologia CMOS 0,35 ?m e incluem: multiplicador de tensão e oscilador em anel, chaveador SPDT (Single Pole Double Through)...

Circuitos integrados de radio-recepção para a operação de multiplexação espacial de antenas em tempo real; Integrated circuits of radio-reception for spatial multiplexing of antennas in real time

Carlos Eduardo Capovilla
Fonte: Biblioteca Digital da Unicamp Publicador: Biblioteca Digital da Unicamp
Tipo: Tese de Doutorado Formato: application/pdf
Publicado em 16/05/2008 PT
Relevância na Pesquisa
66.16%
Esta pesquisa tem por objetivo a concepção de novas topologias de circuitos integrados e suas caracterizações para operação em sistemas de rádio-recepção. O projeto e a fabricação de chaves de RF, LNAs, mixer e VCOs são apresentados. A técnica SMILE (Spatial MultIplexing ofLocal Elements) foi adotada devido às suas vantagens e funcionalidade para a otimização física de antenas inteligentes. Essa técnica requer um chaveamento sequencial das antenas do arranjo e para tal foi desenvolvido um controle de chaveamento acionado por um VCO digital. A demultiplexação analógica do sinal é implementada através de um OTA e chaves analógicas diferenciais. Assim, além da introdução de novas topologias de circuitos integrados, este trabalho estabelece procedimentos de projeto e simulação associados à validação dos dispositivos fabricados. Palavras-chave: circuitos integrados, rádio-recepção, antenas inteligentes, SMILE; This research aims the conception of new topologies of integrated circuits and its characterizations for operation in radio-receiver systems. The design and fabrication of RF switches, LNAs, mixer, and VCOs are presented. The SMILE - Spatial MultIplexing of Local Elements - technique was adopted due to its advantages and functionality for the intelligent antennas physical optimization. This technique requires a sequential switching of the antennas and for this purpose a switch driver with a digital VCO was developed. The analog demultiplexation of the signal is implemented with OTA and differential analog switches. Thus...

Design for manufacturability with regular fabrics in digital integrated circuits; Design for manufactureability with regular fabrics in digital integrated circuits

Gazor, Mehdi (Seyed Mehdi)
Fonte: Massachusetts Institute of Technology Publicador: Massachusetts Institute of Technology
Tipo: Tese de Doutorado Formato: 115 p.; 5441957 bytes; 5446729 bytes; application/pdf; application/pdf
ENG
Relevância na Pesquisa
56.27%
Integrated circuit design is limited by manufacturability. As devices scale down, sensitivity to process variation increases dramatically, making design for manufacturability a critical concern. Designers must identify the designs that generate the least systematic process variation, e.g., from pattern dependent effects, but must also build circuits that are robust to the remaining process or environmental random variations. This research addresses both ideas, by examining integrated circuit design styles and aspects that can help curb process variation and improve manufacturability and performance in future technology generations. One suggested method to reduce variation sensitivity in system designs has been the concept of design regularity. Long used in FPGAs, and SRAMs, the concept of repeatable blocks is examined in this work as a method of reducing circuit variation. Layout based variation is examined in three designs with different distinctions of regularity: a Via-Patterned Gate Array (VPGA) FPU, a Berkeley BEE-generated decoder, and a low power FPGA. The circuit level impact on variation is also considered, by examining several circuit architectures. This includes analysis of the novel Limited Switch Dynamic Logic (LSDL) style...

On-chip resonance in nanoscale integrated circuits

Rosenfeld, Jonathan (1973 - ); Friedman, Eby G.
Fonte: University of Rochester Publicador: University of Rochester
Tipo: Tese de Doutorado Formato: Number of Pages:xxv, 307 leaves.; Illustrations:ill. (some col.)
ENG
Relevância na Pesquisa
66.3%
Thesis (Ph. D.)--University of Rochester. Dept. of Electrical and Computer Engineering, 2009.; Relentless scaling of integrated circuits has resulted in significant performance improvements. Although active devices mostly benefit from scaling, passive interconnect networks have degraded in performance with scaling. Interconnect parasitic effects therefore must be considered throughout the design process. Furthermore, novel and innovative design methodologies for interconnect networks are required to maintain high performance in these highly complex integrated circuits. The focus of this thesis is on three important interconnect networks: clock, data, and power generation and distribution networks. Design and analysis methodologies to improve the performance of these networks have been developed. Specifically, the following three topics have been addressed in this thesis. Exploiting resonance for distributing high frequency clock signals is a promising technology to reduce power dissipation, clock skew, and jitter. A comprehensive methodology for designing these resonant networks has been developed. A case study of a 5 GHz clock signal within a resonant H-tree network has been demonstrated in a 180 nm CMOS technology, resulting in a substantial 84% reduction in power consumption as compared to a traditional H-tree network. On-chip resonance has also been used to design a novel data distribution network. By eliminating the need for traditional buffer insertion...

Switching noise and timing characteristics in nanoscale integrated circuits

Salman, Emre (1981 - ); Friedman, Eby G.
Fonte: University of Rochester Publicador: University of Rochester
Tipo: Tese de Doutorado Formato: Number of Pages:xxxvii, 348 leaves.; Illustrations:ill.
ENG
Relevância na Pesquisa
66.14%
Thesis (Ph. D.)--University of Rochester. Dept. of Electrical and Computer Engineering, 2009.; Continuous progress in the design and manufacturing of integrated circuits (ICs) has enabled the integration of more than two billion transistors on the same die with clock frequencies well above several gigahertz. These improvements have triggered the era of system-on-chip (SoC) and system-in-package (SiP), drastically changing the classical understanding of noise in complex ICs. Traditionally, device noise has been the primary concern for analog ICs while digital ICs have typically been considered to be relatively immune to noise. This situation has changed significantly due to denser integration and faster signal transition times. Specifically, switching noise has become a primary design criterion for both mixed-signal and high performance synchronous digital ICs. Voltage fluctuations on the power/ground nodes of a circuit, i.e., power/ground noise, is a type of switching noise affecting both mixed-signal and digital ICs. A methodology is proposed to accurately estimate the worst case power/ground noise in an inductive power/ground distribution network with a decoupling capacitor. In mixed-signal ICs, power/ground noise affects the highly sensitive analog/RF blocks through the monolithic substrate...

Subharmonic Mixers in CMOS Microwave Integrated Circuits

Jackson, Bradley
Fonte: Quens University Publicador: Quens University
Tipo: Tese de Doutorado Formato: 2978410 bytes; application/pdf
EN; EN
Relevância na Pesquisa
66.07%
This thesis explores the design and applications of subharmonic mixers in CMOS microwave integrated circuits. First, a 2x down-converting subharmonic mixer is demonstrated with a measured conversion gain of 8 dB using a 2.1 GHz RF signal. Extending the concept of the 2x subharmonic mixer, a 4x subharmonic mixer is proposed that operates in the 12 GHz Ku-band. This circuit is the first 4x subharmonic mixer in CMOS, and achieves a 6 dB conversion gain, which is the highest for any 4x subharmonic mixer regardless of circuit topology or fabrication technology. Furthermore, it achieves very high measured isolation between its ports (e.g. 4LO-RF: 59 dB). Since both the 2x and the 4x subharmonic mixers require a quadrature oscillator, a new oscillator circuit is presented that could be used with either of the aforementioned mixers. This quadrature oscillator uses active superharmonic coupling to establish the quadrature fundamental relationship. The oscillation frequency is 3.0 GHz and the measured output power is -6 dBm. A dual-band mixer/oscillator is also demonstrated that can operate as either a fundamental mixer or a subharmonic mixer depending on a control voltage. This circuit operates from 5.0 GHz to 6.0 GHz or from 9.8 GHz to 11.8 GHz by using either the fundamental output or the second harmonic output of the quadrature oscillator circuit described above and achieves conversion gain over both frequency bands. A novel frequency tripler circuit is presented based on a subharmonic mixer. This circuit uses the 2x subharmonic mixer discussed above...

Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis

HE, SHAN
Fonte: Quens University Publicador: Quens University
Tipo: Tese de Doutorado
EN; EN
Relevância na Pesquisa
66.17%
Analog circuits that operate with low voltage supply headroom generally suffer from poor linearity performance, poor noise performance, etc. However, with the aggressive scaling of the supply voltage in Complementary Metal Oxide Semiconductor (CMOS) technology and the advent of System-On-Chip (SOC) technologies, it is inevitable that these circuits are to be operated with low voltage supply headroom. In this thesis, three low-voltage Integrated Circuits (IC) for Radio Frequency (RF) communication systems are presented. They are all designed and fabricated with 0.13um CMOS technology. Their experimental verifications are performed on die with Coplanar Waveguide (CPW) probes. The first circuit is an ultra-low-voltage low-power single-balanced $\times$2 subharmonic down-conversion mixer. A linearity analysis for the inductive source degenerated transconductor of the mixer is provided using Volterra series. This analysis provides a guideline for designing the inductive source degenerated transconductor with high linearity at the RF frequency of 8.6 GHz. The circuit achieves a conversion gain of 6.0 dB and an $IIP_{3}$ of -8.0 dBm at the RF frequency of 8.6 GHz while consuming 0.6 mW of DC power with the supply voltage of 0.6 V. The second circuit is a low-voltage low-noise wideband down-conversion mixing frontend that consists of a Low-Noise Amplifier (LNA) and a passive mixer. The linearity analysis for the LNA...

Ambiente de apoio ao projeto de circuitos integrados baseado no world wide web; A world wide web based integrated circuits design environment

Indrusiak, Leandro Soares
Fonte: Universidade Federal do Rio Grande do Sul Publicador: Universidade Federal do Rio Grande do Sul
Tipo: Dissertação Formato: application/pdf
POR
Relevância na Pesquisa
86.26%
Atualmente, o use de ferramentas de apoio ao projeto de circuitos integrados é indispensável, devido a complexidade desses circuitos que aumenta incessantemente. O presente trabalho discute um modelo para integração de ferramentas em um ambiente único - formando um framework - com o objetivo de acelerar o processo de concepção dos circuitos através da automatização de tarefas, livrando o projetista de tarefas como a administração de recursos distribuídos, o armazenamento de arquivos e assim por diante. 0 framework proposto é baseado em um ambiente amplamente conhecido: o World Wide Web. Ao utilizar o World Wide Web como base para o ambiente de integração de ferramentas, muito trabalho é poupado, uma vez que grande parte da interface gráfica e do controle de rede do framework já esta implementada. A facilidade de acesso ao WWW também é uma grande vantagem, no caso de uma equipe de projeto distribuída. A integração das ferramentas segue dois modelos. O primeiro é utilizado em ferramentas de maior interação com o usuário. Nesse caso, a ferramenta deve ser re-escrita para ser integrada ao ambiente na forma de applets - programas escritos com a linguagem Java que podem ser anexados a documentos WWW. O segundo modelo é utilizado em ferramentas com pouca ou nenhuma interação com o usuário. Essas ferramentas são integradas através de entradas e saídas de dados. Usando applets Java...

6.012 Microelectronic Devices and Circuits, Spring 2003; Microelectronic Devices and Circuits

Del Alamo, Jesus; Scholvin, Jorg
Fonte: MIT - Massachusetts Institute of Technology Publicador: MIT - Massachusetts Institute of Technology
EN-US
Relevância na Pesquisa
56.28%
Modeling of microelectronic devices, and basic microelectronic circuit analysis and design. Physical electronics of semiconductor junction and MOS devices. Relation of electrical behavior to internal physical processes; development of circuit models; and understanding the uses and limitations of various models. Use of incremental and large-signal techniques to analyze and design bipolar and field effect transistor circuits, with examples chosen from digital circuits, single-ended and differential linear amplifiers, and other integrated circuits. Design project. From the course home page: Course Description 6.012 is the header course for the department's "Devices, Circuits and Systems" concentration. The topics covered include: modeling of microelectronic devices, basic microelectronic circuit analysis and design, physical electronics of semiconductor junction and MOS devices, relation of electrical behavior to internal physical processes, development of circuit models, and understanding the uses and limitations of various models. The course uses incremental and large-signal techniques to analyze and design bipolar and field effect transistor circuits, with examples chosen from digital circuits, single-ended and differential linear amplifiers...

A design methodology for application specific fuzzy integrated circuits

Barriga, Angel; Senhadji, Raouf; Jiménez Fernández, Carlos Jesús; Baturone, I.; Sánchez-Solano, Santiago
Fonte: Institute of Electrical and Electronics Engineers Publicador: Institute of Electrical and Electronics Engineers
Tipo: Comunicación de congreso Formato: 83633 bytes; application/pdf
ENG
Relevância na Pesquisa
76.13%
The main objective of this contribution is to present a design methodology for application specific fuzzy integrated circuits. This methodology is based on an specific architecture and a user-friendly design environment which enables the specification, verification and synthesis of fuzzy systems taking into account conceptual as well as microelectronics considerations.; Peer reviewed

Design and fabrication of lateral high power devices for power integrated circuits applications

Talacka, Raymond
Fonte: Rochester Instituto de Tecnologia Publicador: Rochester Instituto de Tecnologia
Tipo: Tese de Doutorado
EN_US
Relevância na Pesquisa
66.1%
The incorporation of high power devices on the same chip as that of the circuitry controlling the high power device has been shown to provide several major advantages over discrete and multichip module designs. The major focus of this work is the development of lateral high power devices that are compatible with R.I.T.'s low power CMOS process. The thrust of this study is to evaluate the feasibility of fabricating Power Integrated Circuits at R.I.T's semiconductor die manufacturing laboratory. As part of the development, several types of high power devices were investigated and the Power MOSFET and IGBT were chosen to be fabricated. The Power MOSFET and IGBT were chosen because they were the least complicated and would provide the greatest probability of functionality. The bulk of the work involved studying the effect of the field plate overlap on the breakdown voltage and the on state resistance. The basic process needed to fabricate the power device was designed and a SUPREM 4 simulation has been generated. The designed process produced a power MOSFET with a breakdown voltage of 50 volts and an operating current of nearly 0.5 amps with an on state resistance of 35Q, while maintaining the standard CMOS operating characteristics for the low power devices. The results are discussed and recommendation for future work at R.I.T. are provided.

Development and evaluation of an intrinsic gettering process for fabrication of integrated circuits

Will, James ii
Fonte: Rochester Instituto de Tecnologia Publicador: Rochester Instituto de Tecnologia
Tipo: Tese de Doutorado
EN_US
Relevância na Pesquisa
76.01%
An internal gettering process to collect and trap potentially harmful defects in the bulk of the silicon wafer, away from the surface where the integrated circuits are fabricated, has been developed in this work. This gettering process was then incorporated into the standard metal gate PMOS process utilized at RIT. Capacitors and diodes were electrically characterized to compare wafers that were gettered versus wafers that were not gettered. Results show that gettering did improve device characteristics, but only in the center of the wafers. The experimental results indicate that the diffusion of impurities from the furnace tube and quartz boat is competing with the gettering process during the lengthy furnace times. As a result, devices near the perimeter of the wafer exhibit poorer electrical characteristics after gettering when compared with the standards. This work shows that gettering will improve device performance, but only when accompanied by attention to furnace contamination. Gettering alone will not guarantee a better device.

Characterization of physical defects and fault analysis of molecular and nanoscaled integrated circuits

Lyshevski, Sergey
Fonte: IEEE Publicador: IEEE
Tipo: Proceedings
EN_US
Relevância na Pesquisa
66.12%
This paper reports a concept to design the defect-tolerant molecular integrated circuits (MICs). The results are applicable to conventional ICs which utilize solid-state devices. By enhancing photolithography and other CMOS processes, advancing materials and optimizing devices, some device and circuit performance were improved. Unfortunately, some key performance characteristics and capabilities were significantly degraded. The performance tradeoffs and effects of the equivalent cell size reduction are well known. The defects and faults at the device and circuit levels must be accommodated. It is illustrated that in general, the defects and faults can be accommodated.; Copyright 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Design of three-dimensional molecular integrated circuits and molecular architectronics

Lyshevski, Sergey
Fonte: IEEE Publicador: IEEE
Tipo: Proceedings
EN_US
Relevância na Pesquisa
66.17%
This paper reports a unified synthesis taxonomy in design of three-dimensional (3D) molecular integrated circuits (MICs). These MICs, fabricated utilizing bottom-up molecular fabrication technologies, are designed as aggregated neuronal hypercells ([unk]hypercell). Each[unk]hypercell is implemented using molecular gates (Mgates) which composed from multi-terminal molecular electronic devices that exhibit and operate due to quantum phenomena. The intelligent library of[unk]hypercell aggregates, [unk]hypercells, Mgates, molecular devices and data-structure primitives can be developed and utilized. To address complexity and technology dependence, this paper documents innovative methods in design, optimization, evaluation and verification of 3DMICs. The logic design of MICs is accomplished by using a novel technology-centric concept based on the use of[unk]hypercells and linear decision diagrams. We initiate the developments of a 3D super-large-scale integration (3DSLSI) design concept. This paper reports a proof-of-concept CAD design tools illustrating and verifying the results for combinational MICs.; Copyright 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists...

Information-theoretic analysis of three-dimensional molecular integrated circuits

Lyshevski, Sergey
Fonte: IEEE Publicador: IEEE
Tipo: Proceedings
EN_US
Relevância na Pesquisa
66.11%
For three-dimensional (3D) molecular integrated circuits (MICs), an information-theoretic model of signal processing is under developments in order. The objective is to estimate and examine the information-theoretic measures in order to perform optimization and carry out optimal design. Distinct information measures, such as entropy, capacity, complexity and other are analyzed. There is a need to derive baseline information estimates for 3DMICs to optimize molecular hardware and ensure a technology-centric co-design. This will allow us to approach fundamental limits and benchmarks. Three-dimensional MICs are envisioned to implement datapath, memory and other subsystems. For information measures, different quantitative and qualitative estimates can be utilized. The information-theoretic analysis imposes significant challenges due to mathematical complexity and technology dependence. The information analysis to correctly compute switching functions and maximize the mutual information examining channel input and output can be performed. However, digital versus analog solutions, switching frequency, thresholds, switching energy, power losses and other characteristics depend on logic design as well as dynamic and steady-state characteristics of molecular devices. Hence...

Three dimensional multi-valued design in nanoscale integrated circuits

Lyshevski, Sergey
Fonte: IEEE Publicador: IEEE
EN_US
Relevância na Pesquisa
66.08%
Novel three-dimensional (3D) nanoscale integrated circuits (nanoICs) are examined in this paper. These nanoICs are synthesized utilizing aggregated 3D neuronal-hypercells (ℵ-hypercells) with multi-terminal electronic nanodevices. The proposed nanodevices ensure multi-valued input-output characteristic that lead to a direct technological solution of multi-valued logic synthesis problem. Super-high-performance computing architectures and memories can be devised (synthesized), designed and optimized. At the system-level, we examine nanoICs as networked aggregated 3D ℵ-hypercells. In particular, scalable 3D ℵ-hypercell topologies are under consideration. These ℵ-hypercells integrate interconnected functional multi-terminal electronic nanodevices that implement logic functions. The proposed nanoICs platform suits the envisioned cognizant computing ensuring preeminent information processing and immense memory.; Copyright 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.; Proceedings of the 35th International Symposium on Multiple-Valued Logic (ISMVL’05)

Subthreshold circuits: Design, implementation and application

Kanitkar, Hrishikesh
Fonte: Rochester Instituto de Tecnologia Publicador: Rochester Instituto de Tecnologia
Tipo: Tese de Doutorado
EN_US
Relevância na Pesquisa
66.04%
Digital circuits operating in the subthreshold region of the transistor are being used as an ideal option for ultra low power complementary metal-oxide-semiconductor (CMOS) design. The use of subthreshold circuit design in cryptographic systems is gaining importance as a counter measure to power analysis attacks. A power analysis attack is a non-invasive side channel attack in which the power consumption of the cryptographic system can be analyzed to retrieve the encrypted data. A number of techniques to increase the resistance to power attacks have been proposed at algorithmic and hardware levels, but these techniques suffer from large area and power overheads. The main aim of this research is to understand the viability of implementing subthreshold systems for cryptographic applications. Standard cell libraries in subthreshold are designed and a methodology to identify the minimum energy point, aspect ratio, frequency range and operating voltage for CMOS standard cells is defined. As scalar multiplication is the fundamental operation in elliptic curve cryptographic systems, a digit-level gaussian normal basis (GNB) multiplier is implemented using the aforementioned standard cells. A similar standard-cell library is designed for the multiplier to operate in the superthreshold regime. The subthreshold and superthreshold multipliers are then subjected to a differential power analysis attack. Power performance and signal-to-noise ratio (SNR) of both these systems are compared to evaluate the usefulness of the subthreshold design. The power consumption of the subthreshold multiplier is 4.554 uW...

Design and implementation of a computational cluster for high performance design and modeling of integrated circuits

Gruener, Charles J.
Fonte: Rochester Instituto de Tecnologia Publicador: Rochester Instituto de Tecnologia
Tipo: Tese de Doutorado
EN_US
Relevância na Pesquisa
66.24%
Modern microelectronic engineering fabrication involves hundreds of processing steps beginning with design, simulation and modeling. Tremendous data is acquired, managed and processed. Bringing together Information Technology (IT) into a functional system for microelectronic engineering is not a trivial task. Seamless integration of hardware and software is necessary. For this purpose, knowledge of design and fabrication of microelectronic devices and circuits is extremely important along with knowledge of current IT systems. This thesis will explain a design methodology for building and using a computer cluster running software used in the production of microelectronic circuits. The cluster will run a Linux operating system to support software from Silvaco and Cadence. It will discuss the selection, installation, and verification of hardware and software based on defined goals. The system will be tested via numerous methods to show proper operation, focusing on TCAD software from Silvaco and custom IC design software from Cadence. To date, the system has been successfully tested and performs well. Since the target applications are doing simulations that are independent of each other, parallelization is very easy and user friendly. By simply adding more computers with more CPUs...