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Geração de processador para aplicacao especifica; Application specific processor generation

Kreutz, Marcio Eduardo
Fonte: Universidade Federal do Rio Grande do Sul Publicador: Universidade Federal do Rio Grande do Sul
Tipo: Dissertação Formato: application/pdf
POR
Relevância na Pesquisa
105.84%
Este trabalho propõe a geração de uma arquitetura dedicada a aplicações específicas, baseadas no microcontrolador MCS8051. Por ser utilizado na solução de problemas em indústrias locais, este processador foi escolhido para servir como base em um sistema dedicado. O 8051 dedicado gerado deverá permitir a integração completa do sistema, proporcionando um aumento do valor agregado e, conseqüentemente, a diminuição do custo. Busca-se com a otimização da arquitetura obter um conjunto de instruções reduzido, construído com as instruções mais utilizadas em cada aplicação. O objetivo principal da otimização do conjunto de instruções está relacionado ao fato de que os circuitos decodificadores e geradores de microcódigo da parte de controle ocupam uma área significativa do processador. Uma otimização no sentido de reduzir-se o conjunto de instruções, portanto, resulta numa economia de área, o que vem de encontro com a idéia da integração completa do sistema com o processador. Um processador dedicado a aplicações específicas (ASIP) irá possuir um custo maior do que a sua versão original, devido as otimizações realizadas. Para compensar este custo, uma alternativa a seguir é a integração completa do sistema. Um Sistema Integrado para Aplicações Específicas (SIAE) torna-se desejável...

Implementação física de arquiteturas de hardware para a decodificação de vídeo digital segundo o padrão H.264/AVC; Physical implementation of hardware architectures for video decoding according to the H.264/AVC standard

Silva, Leandro Max de Lima
Fonte: Universidade Federal do Rio Grande do Sul Publicador: Universidade Federal do Rio Grande do Sul
Tipo: Dissertação Formato: application/pdf
POR
Relevância na Pesquisa
45.74%
Recentemente, o Brasil adotou o padrão SBTVD (Sistema Brasileiro de TV Digital) para transmissão de TV digital. Este utiliza o CODEC (codificador e decodificador) de vídeo H.264/AVC, que é considerado o estado-da-arte no contexto de compressão de vídeo digital. Esta transição para o SBTVD requer o desenvolvimento de tecnologia para transmissão, recepção e decodificação de sinais, assim, o projeto Rede H.264 SBTVD foi iniciado e tem como um dos objetivos a produção de componentes de hardware para construção de um set-top box SoC (System on Chip) compatível com o SBTVD. No sentido de produzir IPs (Intellectual Property) para codificação e decodificação de vídeo digital segundo o padrão H.264/AVC, várias arquiteturas de hardware vêm sendo desenvolvidas no âmbito do projeto. Assim, o objetivo deste trabalho consiste na realização da implementação física em ASIC (Application-Specific Integrated Circuit) de algumas destas arquiteturas de hardware para decodificação de vídeo H.264/AVC, entre elas as arquiteturas parser e decodificação de entropia, predição intra-quadro e, por fim, quantização e transformadas inversas, que juntas formam uma versão funcional de um decodificador de vídeo H.264 chamado de decodificador intra-only. Além destas...

Metodologia e projeto de ferramenta para co-simulação entre VHDL e SystemC; Methodology and design of a tool to co-simulate VHDL and SystemC

Richard Maciel Costa
Fonte: Biblioteca Digital da Unicamp Publicador: Biblioteca Digital da Unicamp
Tipo: Dissertação de Mestrado Formato: application/pdf
Publicado em 15/08/2008 PT
Relevância na Pesquisa
35.77%
Em um passado recente os sistemas eram constituídos de partes discretas tais como microprocessadores, memórias e Application Specific Integrated Circuits (ASICs). Essa separação clara e simples tornava possível a especificação ser feita por uns poucos projetistas utilizando uma abordagem top-down: a partir de um modelo comportamental ou Register-Transfer Level (descritos em VHDL, por exemplo), progressivamente refinando o modelo ate o nível Transistor-to-Transistor. Entretanto, o avanço contínuo do processo de miniaturização de transistores possibilitou a criação de sistemas completos integrados em um único chip (também chamados de System-on-chip). Dado que esses sistemas s~ao tipicamente constituídos por diversos componentes complexos, um nível mais alto de abstração - o de sistema - foi criado, juntamente com suas linguagens associadas (como a linguagem SystemC), para facilitar o trabalho dos projetistas. As linguagens utilizadas para modelar no nível de sistema são diferentes das linguagens utilizadas para modelar nos níveis comportamental e Register-Transfer. Assim, surge o problema de como co-verificar componentes descritos em diferentes níveis de abstração; característica desejável para projetos de grande porte...

Uma contribuição sobre a análise dos aspectos tecnológicos, estruturasis e comportamentais na implementação de sistemas de informação integrados; A contribution on the analysis of technological, structural and behavior aspects in the implementation of integrated information systems

Adalberto Fernandes de Oliveira
Fonte: Biblioteca Digital da Unicamp Publicador: Biblioteca Digital da Unicamp
Tipo: Dissertação de Mestrado Formato: application/pdf
Publicado em 29/07/2010 PT
Relevância na Pesquisa
35.72%
Esse trabalho tem como objetivo analisar os aspectos tecnológicos, estruturais e comportamentais ocasionados pela decisão da implementação e utilização de um sistema de manufatura integrado por sistemas de informação. Neste trabalho foi desenvolvido uma sequência de etapas para a implementação de sistemas de informação integrados, capazes de apoiar os diversos processos de um ambiente de fábrica, o qual apresenta benefícios significativos para o sistema de gestão. O entendimento de como estruturar os sistemas de informação de forma integrada para dar apoio ao sistema de manufatura, é adquirido através da compreensão de cada campo de conhecimento em específico (estratégia, planejamento estratégico, sistemas de manufatura, sistemas de informação e empresa integrada) para num segundo passo agrupá-los em um contexto único, do qual todos fazem parte. A análise dos aspectos foi realizada através de múltiplos estudos de casos com aplicação da proposta em empresas de diferentes segmentos. Os resultados da análise nesse trabalho demonstrou que a implementação de sistemas de informação integrados para dar apoio ao sistema de manufatura, traz muitos benefícios e inovações que são capazes de contribuir para um estado de competitividade...

A New Statistics-Based Online Baseline Restorer for a High Count-Rate Fully Digital System

Li, Hongdi; Wang, Chao; Baghaei, Hossain; Zhang, Yuxuan; Ramirez, Rocio; Liu, Shitao; An, Shaohui; Wong, Wai-Hoi
Fonte: PubMed Publicador: PubMed
Tipo: Artigo de Revista Científica
Publicado em /04/2010 EN
Relevância na Pesquisa
45.64%
The goal of this work is to develop a novel, accurate, real-time digital baseline restorer using online statistical processing for a high count-rate digital system such as positron emission tomography (PET). In high count-rate nuclear instrumentation applications, analog signals are DC-coupled for better performance. However, the detectors, pre-amplifiers and other front-end electronics would cause a signal baseline drift in a DC-coupling system, which will degrade the performance of energy resolution and positioning accuracy. Event pileups normally exist in a high-count rate system and the baseline drift will create errors in the event pileup-correction. Hence, a baseline restorer (BLR) is required in a high count-rate system to remove the DC drift ahead of the pileup correction. Many methods have been reported for BLR from classic analog methods to digital filter solutions. However a single channel BLR with analog method can only work under 500 kcps count-rate, and normally an analog front-end application-specific integrated circuits (ASIC) is required for the application involved hundreds BLR such as a PET camera. We have developed a simple statistics-based online baseline restorer (SOBLR) for a high count-rate fully digital system. In this method...

Spatial variability of crop and soil properties in a crop-livestock integrated system.

ANDRADE, R. G.; BERNARDI, A. C. de C.; GREGO, C. R.; INAMASU, R. Y.; RABELLO, L. M.; VAZ, C. M. P.
Fonte: In: INTERNATIONAL CONFERENCE ON PRECISION AGRICULTURE, 10., 2010. Denver, CO. Anais... Denver, CO: Colorado State: IPNI: FAR, 2010. Publicador: In: INTERNATIONAL CONFERENCE ON PRECISION AGRICULTURE, 10., 2010. Denver, CO. Anais... Denver, CO: Colorado State: IPNI: FAR, 2010.
Tipo: Artigo em anais de congresso (ALICE)
EN
Relevância na Pesquisa
45.67%
The knowledge of spatial variability soil properties is useful in the rational use of inputs, as in the site specific application of lime and fertilizer. The objective of this work was to map and evaluate the spatial variability of the corn and pasture, soil chemical and physical properties in crop-livestock integrated system. The study was conducted in an area of 6.9 ha of a Typic Paleudult in Sao Carlos, SP, Brazil. The summer crop corn was sowed together with the forage crop Brachiaria brizantha in the system of crop-livestock rotation. A regular hexagon sampling grid design with 6 sub-samples was adopted for each hectare. The values of soil P, K, Ca, Mg, and CEC, basis saturation, clay and sand were analyzed by traditional soil testing in georreferenced samples collected at 0?0.2 m depth. Soil electrical conductivity (EC) was measured with a contact sensor. The site was evaluated at the end of the corn season (April) and for the forage (October) by imageries from the Landsat 5 using remote sensing techniques and a geographic information system. Normalized difference vegetation index (NDVI) was used to interpret imageries. Spatial continuity of crop and soil properties was modeled using semivariograms. Maps contours of crop and forage were obtained by kriging...

VLSI testing and characterization system for micro electro-mechanical (MEM) sensors

Yao, Junfang
Fonte: FIU Digital Commons Publicador: FIU Digital Commons
Tipo: Artigo de Revista Científica
EN
Relevância na Pesquisa
45.57%
The purpose of this investigation was to develop and implement a general purpose VLSI (Very Large Scale Integration) Test Module based on a FPGA (Field Programmable Gate Array) system to verify the mechanical behavior and performance of MEM sensors, with associated corrective capabilities; and to make use of the evolving System-C, a new open-source HDL (Hardware Description Language), for the design of the FPGA functional units. System-C is becoming widely accepted as a platform for modeling, simulating and implementing systems consisting of both hardware and software components. In this investigation, a Dual-Axis Accelerometer (ADXL202E) and a Temperature Sensor (TMP03) were used for the test module verification. Results of the test module measurement were analyzed for repeatability and reliability, and then compared to the sensor datasheet. Further study ideas were identified based on the study and results analysis. ASIC (Application Specific Integrated Circuit) design concepts were also being pursued.^

Design techniques for low power mixed analog-digital circuits with application to smart wireless systems.

Al-Sarawi, Said Fares Khalil
Fonte: Universidade de Adelaide Publicador: Universidade de Adelaide
Tipo: Tese de Doutorado
Publicado em //2003
Relevância na Pesquisa
45.65%
This dissertation presents and discusses new design techniques for mixed analog-digital circuits with emphases on low power and small area for standard low-cost CMOS VLSI technology. The application domain of the devised techniques is radio frequency identification (RFID) systems, however the presented techniques are applicable to wide range of mixed mode analog-digital applications. Hence the techniques herein apply to a range of smart wireless or mobile systems. The integration of both analog and digital circuits on a single substrate has many benefits such as reducing the system power, increasing the system reliability, reducing the system size and providing high inter-system communications speed - hence, a cost effective system implementation with increased performance. On the other hand, some difficulties arise from the fact that standard low-cost CMOS technologies are tuned toward maximising digital circuit performance and increasing transistor density per unit area. Usually these technologies have a wide spread in transistor parameters that require new design techniques that provide circuit characteristics based on relative transistor parameters rather than on the absolute value of these parameters. This research has identified new design techniques for mostly analog and some digital circuits for implementation in standard CMOS technologies with design parameters dependent on the relative values of process parameters...

Eine Systemumgebung zur Erstellung paralleler C++ Programme und deren Ausführung in heterogenen verteilten Systemen; A System Environment for the Creation of Parallel C++ Programs and their Execution in Heterogeneous Distributed Systems

Blochinger, Wolfgang
Fonte: Universidade de Tubinga Publicador: Universidade de Tubinga
Tipo: Dissertação
DE_DE
Relevância na Pesquisa
45.63%
Diese Arbeit behandelt die Realisierung und die Anwendung der Systemumgebung DOTS (Distributed Object-Oriented Threads System) zur Erstellung paralleler C++ Programme. DOTS verwirklicht insbesondere spezielle Anforderungen zur Parallelisierung von Algorithmen aus dem Bereich des symbolischen Rechnens. Die effiziente Parallelisierung der sich typischerweise rasch fortentwickelnden sequentiellen Verfahren des symbolischen Rechnens wird durch das von DOTS realisierte parallele Programmiermodell des strikten Multithreading im besonderem Maße unterstützt. Die hohe Abstraktionsebene dieses Modells gewährleistet die weitgehende Übernahme der sequentiellen Entwicklungsmethodik und ermöglicht somit die schnelle und einfache Erstellung paralleler Programme ausgehend von einer sequentiellen Codebasis. Das Programmiermodell ist durch eine kompakte Programmierschnittstelle mit vollständig orthogonal verwendbaren Primitiven verwirklicht. Die Behandlung des oftmals anzutreffenden hohen Grads an Nichtdeterminismus der parallelisierten Programme wird durch die Integration spezieller Primitive in das Programmiermodell des strikten Multithreading von DOTS berücksichtigt. DOTS wurde zur Erstellung paralleler C++ Programme entwickelt, die in heterogenen verteilten Systemen ausgeführt werden können. Die Laufzeitumgebung von DOTS integriert ein breites Spektrum von Rechnerarchitekturen und Betriebssystemen (Microsoft Windows PCs...

Efficient Distributed Bounded Property Checking; Effiziente verteilte begrenzte Eigenschaftspruefung

Nalla, Pradeep Kumar
Fonte: Universidade de Tubinga Publicador: Universidade de Tubinga
Tipo: Dissertação
EN
Relevância na Pesquisa
35.73%
Today, verification of industrial size designs like multi-million gate ASICs (Application Specific Integrated Circuit) and SoC (System-on-a-Chip) processors consumes up to 75%of the design effort. The trend to augment functional verification with formal verification tries to alleviate this problem. Efficient property checking algorithms based on binary decision diagrams (BDDs) and satisfiability (SAT) solvers allow the automatic verification of medium-sized designs. However, the steadily increasing design sizes still leave verification as the major bottleneck, because formal methodologies do not yet scale to very large designs. To address these problems researchers came up with the idea of combining symbolic simulation and bounded model checking on-the-fly. The current tools pioneer in handling comparatively larger designs by partitioning the state set and they can be represented using partitioned ordered BDDs (POBDDs). These partitions will be explored in a divide-and-conquer manner. However, still they face memory exhaustion for very large models due to the BDD explosion problem. Even the SAT based bounded model checking (BMC) can search up to a maximum depth allowed by the physical memory on a single server. These observations motivated the parallelization of symbolic state space traversal algorithms. Distributed algorithms verify larger models and return results faster than sequential versions. Existing schemes for parallelizing BDD-based verification algorithms often suffer from state overlap or duplicate work...

High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm

Sun, Yang; Cavallaro, Joseph R.
Fonte: IEEE Publicador: IEEE
Tipo: Artigo de Revista Científica
ENG
Relevância na Pesquisa
45.5%
In this paper, we propose a novel path-preserving trellis-search (PPTS) algorithm and its high-speed VLSI architecture for soft-output multiple-input-multiple-output (MIMO) detection. We represent the search space of the MIMO signal with an unconstrained trellis, where each node in stage of the trellis maps to a possible complex-valued symbol transmitted by antenna. Based on the trellis model, we convert the soft-output MIMO detection problem into a multiple shortest paths problem subject to the constraint that every trellis node must be covered in this set of paths. The PPTS detector is guaranteed to have soft information for every possible symbol transmitted on every antenna so that the log-likelihood ratio (LLR) for each transmitted data bit can be more accurately formed. Simulation results show that the PPTS algorithm can achieve near-optimal error performance with a low search complexity. The PPTS algorithm is a hardware-friendly data-parallel algorithm because the search operations are evenly distributed among multiple trellis nodes for parallel processing. As a case study, we have designed and synthesized a fully-parallel systolic-array detector and two folded detectors for a 4x4 16-QAM system using a 1.08 V TSMC 65-nm CMOS technology.With a 1.18 mm2 core area...

Architecture of an integrated microelectronic warfare system on a chip and design of key components

Luke, Brian L.
Fonte: Monterey, California. Naval Postgraduate School Publicador: Monterey, California. Naval Postgraduate School
Relevância na Pesquisa
45.65%
Approved for public release; distribution in unlimited.; This dissertation investigates a mixed-signal, electronic warfare (EW) system-on-a-chip (SoC) design capable of synthesizing false radar returns in response to imaging radar interrogations that, when integrated into the range-Doppler processing, form an image of a false target. Detailed designs for the EW SoC components including the false target digital image synthesizer (DIS) and a novel analog to digital converter (ADC) are provided in this research. Alternative DIS architectures are presented that reduce circuit die area and power dissipation. This research also describes the theory, design, implementation, simulation, and testing of a proof-of-concept application-specific integrated circuit (ASIC) providing automatic counterflow-clock pipeline skew control for the DIS. High performance ADCs are key components of mixed-signal SoCs. Design and simulation results for an 8-bit 1 GS/s robust symmetric number system (RSNS) folding ADC are presented. The gray-code properties of the RSNS make it desirable for error control and low-power ADC implementations. A complete mathematical description of the N-modulus RSNS redundancies is discovered, which results in closed-form expressions for the longest sequence of unique RSNS vectors for moduli of the form m - 1...

An all-digital image synthesizer for countering high-resolution imaging radars

Pace, Phillip E.; Ekestrom, S.; Karow, C.; Fouts, D.
Fonte: Naval Postgraduate School Publicador: Naval Postgraduate School
Tipo: Relatório
EN_US
Relevância na Pesquisa
65.69%
A digital image ssynthesizer (DIS), especially useful as a counter-targeting signal repeater, (i.e., for synthesizing the characteristic echo signature of a pre-selected target) is reported. The DIS has a digital radio frequency memory (DRFM) and associated circuitry, including digital tapped delay lines and a modulator in each delay line to impose both amplitude and frequency modulation in each line. A unique property of the digital image synthesizer is its ability to synthesize false targets using wideband chirp signals of any duration. To generate the target, the user can program the target extent (number of taps) and the amplitude and Doppler frequency of each range-Doppler cell within the image. The system-on-a-chip uses a scalable CMOS technology that increases the bandwidth and sensitivity of such a repeater over prior analog based systems. The application specific integrated circuit reduces the noise of the repeated signal, reduces the size and cost of such a system, and permits real time alteration of operating parameters, permitting rapid and adaptive shifting among different types of targets to be synthesized. A scan path test capability is also included to allow intre-schip signal analysis and verification.

Integrated conservation strategy of built heritage: traditional construction systems and natural materials; Estratégia de conservação integrada do património edificado: sistemas construtivos tradicionais e materiais naturais

Costa, Alice Maria Tavares Alves da
Fonte: Universidade de Aveiro Publicador: Universidade de Aveiro
Tipo: Tese de Doutorado
ENG
Relevância na Pesquisa
35.76%
The risk of losing ancient construction systems is highly relevant in the whole Mediterranean region, but also in many other countries worldwide. The earthen heritage and the mixed construction systems with timber are decreasing very fast and being identified in lists of risk by UNESCO, ICOMOS and by many researchers all over the world. They represent a cultural value of the societies that is being neglected due to unbalanced development, demolitions, lack of knowledge, and guidelines for conservation, instead of the expected unique reason of decay due to natural agents or ageing. Although some conservation approaches have been successful, the results are still scarce and the mistakes continuously repeated imposing irreversible gaps in reading this relevant heritage, mainly in urban areas. This entails questions about the approach to protection, conservation, and the reasons behind such disseminated failure in these objectives. The earthen architecture shows precisely the difficulties in the establishment of a strategy able to successfully achieve the goal of preserving its cultural value. This needs continuous research and ability to communicate the best conservation strategy as just one of the steps of a balanced framework. This investigation aims to discover reasons for failure of conservation strategies involving the traditional construction systems...

Projeto de um codificador/decodificador Viterbi integrado; Integrated Viterbi encoder/decoder design

Pacheco, Roberto Vargas
Fonte: Universidade Federal do Rio Grande do Sul Publicador: Universidade Federal do Rio Grande do Sul
Tipo: Dissertação Formato: application/pdf
POR
Relevância na Pesquisa
45.69%
Com o aumento da densidade de transistores devido aos avanços na tecnologia de fabricação de IC, que usam cada vez dimensões menores e a possibilidade de projetar chips cada vez mais complexos, ASIC (Application Specific Integrated Circuit) podem de fato integrar sistemas complexos em um chip, chamado de System-on-chip. O ASIC possibilita a implementação de processos (módulos) paralelos em hardware, que possibilitam atingir as velocidades de processamento digital necessárias para as aplicações que envolvem altas taxas de dados. A implementação em hardware do algoritmo Viterbi é o principal foco dessa dissertação. Este texto mostra uma breve explicação do algoritmo e mostra os resultados desta na implementação do algoritmo em software e hardware. Uma arquitetura com pipeline é proposta e uma implementação em HDL (Hardware Description Language) é mostrada.; With the increasing density of gates due to advances in the IC manufacturing technology that uses increasingly smaller feature sizes, and the possibility to design more complex systems, ASIC's (Application Specific Integrated Circuit) can in fact integrate complete systems in a single chip, namely Sysntem-on-chip. The ASIC allows the implementation of parallel processes in hardware that makes possible to reach the necessary speed for the applications that need high data rates. The hardware implementation of the Viterbi encoder algorithm is the main focus of this dissertation. The text gives a brief tutorial of the algorithm and shows the results of its implementation in software and in hardware. A pipelined architecture is proposed and implemented in HDL.

Providing an integrated clinical data view in a hospital information system that manages multimedia data.

Dayhoff, R. E.; Maloney, D. L.; Kenney, T. J.; Fletcher, R. D.
Fonte: American Medical Informatics Association Publicador: American Medical Informatics Association
Tipo: Artigo de Revista Científica
Publicado em //1991 EN
Relevância na Pesquisa
35.72%
The VA's hospital information system, the Decentralized Hospital Computer Program (DHCP), is an integrated system based on a powerful set of software tools with shared data accessible from any of its application modules. It includes many functionally specific application subsystems such as laboratory, pharmacy, radiology, and dietetics. Physicians need applications that cross these application boundaries to provide useful and convenient patient data. One of these multi-specialty applications, the DHCP Imaging System, integrates multimedia data to provide clinicians with comprehensive patient-oriented information. User requirements for cross-disciplinary image access can be studied to define needs for similar text data access. Integration approaches must be evaluated both for their ability to deliver patient-oriented text data rapidly and their ability to integrate multimedia data objects. Several potential integration approaches are described as they relate to the DHCP Imaging System.

Investigation of an Intelligent System for Fiber Optic-Based Epidural Anesthesia

Gong, Cihun-Siyong Alex; Ting, Chien-Kun
Fonte: Hindawi Publishing Corporation Publicador: Hindawi Publishing Corporation
Tipo: Artigo de Revista Científica
EN
Relevância na Pesquisa
45.56%
Even though there have been many approaches to assist the anesthesiologists in performing regional anesthesia, none of the prior arts may be said as an unrestricted technique. The lack of a design that is with sufficient sensitivity to the targets of interest and automatic indication of needle placement makes it difficult to all-round implementation of field usage of objectiveness. In addition, light-weight easy-to-use realization is the key point of portability. This paper reports on an intelligent system of epidural space identification using optical technique, with particular emphasis on efficiency-enhanced aspects. Statistical algorithms, implemented in a dedicated field-programmable hardware platform along with an on-platform application-specific integrated chip, used to advance real-time self decision making in needle advancement are discussed together with the feedback results. Clinicians' viewpoint of improving the correct rate of our technique is explained in detail. Our study demonstrates not only that the improved system is able to behave as if it is a skillful anesthesiologist but also it has potential to bring promising assist into clinical use under varied conditions and small amount of sample, provided that several concerns are addressed.

Level-1 Regional Calorimeter Trigger System for CMS

Chumney, P.; Dasu, S.; Lackey, J.; Jaworski, M.; Robl, P.; Smith, W. H.
Fonte: Universidade Cornell Publicador: Universidade Cornell
Tipo: Artigo de Revista Científica
Publicado em 16/05/2003
Relevância na Pesquisa
45.56%
The Compact Muon Solenoid (CMS) calorimeter regional trigger system is designed to detect signatures of isolated and non-isolated electrons/photons, jets, ?-leptons, and missing and total transverse energy using a deadtimeless pipelined architecture. This system contains 18 crates of custom-built electronics. The pre-production prototype backplane, boards, links and Application-Specific Integrated Circuits (ASICs) have been built and their performance is characterized.; Comment: Talk from the 2003 Computing in High Energy and Nuclear Physics (CHEP03), La Jolla, Ca, USA, March 2003, 6 pages, PDF. PSN THHT003

The RIT IEEE-488 buffer design

Connor, John
Fonte: Rochester Instituto de Tecnologia Publicador: Rochester Instituto de Tecnologia
Tipo: Tese de Doutorado
EN_US
Relevância na Pesquisa
45.5%
This document describes the design of an NMOS ASIC used to control an RIT IEEE-488 Buffer previously designed by the author. Past designs used discrete components to implement an asynchronous controller and a synchronous, one-hot controller. The present design utilizes a multiple controller architecture incorporated within the ASIC. The ASIC is used to control bus protocol, bus transceivers, and memory. At power-up, the buffer configures itself as an active listener on the bus and waits for a talker to initiate communication. The buffer accepts a data file (a plot file for example) from the talker, then takes control of the bus, addresses a listener, transfers the stored data to the listener, unaddresses the listener, releases the bus, and finally, reassumes the active listener configuration. The RIT IEEE-488 buffer can realize time savings for a user in a controllerless system. The buffer accepts data from a talker in a matter of seconds and then takes on the chore of driving a slow listener. Thus, the talker is returned quickly to the operator for further use. At present, the buffer isn't queueable - it cannot accept another data file until it completes the transfer of the present file. The author has also added five nmos cells (schematic/layout) into the '/user/pub' directory on the Apollo workstations in the Computer Engineering Department's VLSI LAB at RIT. Cell names are VSCLK...

Trusted software engine and PCB design for data consistency checking of commercial off-the-shelf (COTS) hardware

DelVecchio, Raymond
Fonte: University of Delaware Publicador: University of Delaware
Tipo: Tese de Doutorado
Relevância na Pesquisa
45.57%
Kiamilev, Fouad; Recent trends in technology have pushed the majority of ASIC fabrication overseas. This high volume market leaves devices vulnerable to attack by adversaries who could potentially alter the design at the hardware level while at the foundry. This type of emerging threat, known as a hardware Trojan, can leave mission critical government or financial systems vulnerable to attacks that can lead to system failure. For much of the previous decade, software was the main focus of computer security, but the past few years have ushered in a new wave of hardware security research to safeguard against such attacks. This thesis provides insight into how hardware Trojans are classified, in addition to providing examples of exploits that can lead to sensitive information leakage in an encryption system. A Trojan detection system is proposed for a COTS AES encryption component, which is accompanied by a modular stacked PCB design to implement such a system.; University of Delaware, Department of Electrical and Computer Engineering; M.S.