Página 1 dos resultados de 17114 itens digitais encontrados em 0.020 segundos

Junctionless Multiple-Gate Transistors for Analog Applications

DORIA, Rodrigo Trevisoli; PAVANELLO, Marcelo Antonio; TREVISOLI, Renan Doria; SOUZA, Michelly de; LEE, Chi-Woo; FERAIN, Isabelle; AKHAVAN, Nima Dehdashti; YAN, Ran; RAZAVI, Pedram; YU, Ran; KRANTI, Abhinav; COLINGE, Jean-Pierre
Fonte: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC Publicador: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Tipo: Artigo de Revista Científica
ENG
Relevância na Pesquisa
36.56%
This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width W(fin) and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage V(EA) and larger intrinsic voltage gain A(V) than IM devices of similar dimensions. In addition, V(EA) and A(V) are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.; Science Foundation Ireland[05/IN/I888]; Program for Research in Third-Level Institutions; European Community (EC)[216171]; European Community (EC)[216373]; CAPES; FAPESP; CNPq

Modelagem, simulação e fabricação de circuitos analógicos com transistores SOI convencionais e de canal gradual operando em temperaturas criogênicas.; Modeling, simulation and fabrication of analog circuits with standard and graded-channel SOI transistors operating at cryogenic temperatures.

Souza, Michelly de
Fonte: Biblioteca Digitais de Teses e Dissertações da USP Publicador: Biblioteca Digitais de Teses e Dissertações da USP
Tipo: Tese de Doutorado Formato: application/pdf
Publicado em 16/10/2008 PT
Relevância na Pesquisa
36.61%
Neste trabalho apresentamos a análise do comportamento analógico de transistores MOS implementados em tecnologia Silício sobre Isolante (SOI), de canal gradual (GC) e com tensão mecânica aplicada ao canal, operando em baixas temperaturas (de 380 K a 90 K), em comparação com dispositivos SOI convencionais. Este estudo foi realizado utilizando-se medidas experimentais de transistores e pequenos circuitos fabricados, bem como através da utilização de simulações numéricas bidimensionais e modelos analíticos. No caso dos transistores de canal gradual, inicialmente foi proposto um modelo analítico contínuo para a simulação da corrente de dreno em baixas temperaturas. Este modelo foi validado para temperaturas entre 300 K e 100 K e incluído na biblioteca de modelos de um simulador de circuitos. Foram analisadas características importantes para o funcionamento de circuitos analógicos, tais como a distorção harmônica de dispositivos operando em saturação e o descasamento de alguns parâmetros, como tensão de limiar e corrente de dreno, em diversas temperaturas. No caso da distorção, foi verificada uma melhora significativa promovida pela utilização da estrutura de canal gradual, ultrapassando 20 dB em 100 K. O descasamento apresentou piora em relação ao transistor convencional...

Mixed-signal analog-digital circuits design on the pre-diffused digital array using trapezoidal association of transistors

Choi, Jung Hyun
Fonte: Universidade Federal do Rio Grande do Sul Publicador: Universidade Federal do Rio Grande do Sul
Tipo: Tese de Doutorado Formato: application/pdf
ENG
Relevância na Pesquisa
36.7%
The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent single transistors. Basic analog cells were also designed as well in full-custom and TAT versions in 1.0mm and 0.5mm digital CMOS technologies. Most of the circuits were prototyped in full-custom and TAT-based on pre-diffused SOT arrays. An innovative demonstration of the TAT technique is shown with the design and implementation of a mixed-signal analog system, i. e., a fully differential 2nd order Sigma-Delta Analog-to-Digital (A/D) modulator, fabricated in both full-custom and SOT array methodologies in 0.5mm CMOS technology from MOSIS foundry. Three test-chips were designed and fabricated in 0.5mm. Two of them are IC chips containing the full-custom and SOT array versions of a 2nd-Order Sigma-Delta A/D modulator. The third IC contains a transistors-structure (TAT and single) and analog cells placed side-by-side...

Low cost BIST techniques for linear and non-linear analog circuits; Técnicas de teste embarcado de baixo custo para circuitos analógicos lineares e não-lineares

Negreiros, Marcelo
Fonte: Universidade Federal do Rio Grande do Sul Publicador: Universidade Federal do Rio Grande do Sul
Tipo: Tese de Doutorado Formato: application/pdf
ENG
Relevância na Pesquisa
36.81%
With the ever increasing demands for high complexity consumer electronic products, market pressures demand faster product development and lower cost. SoCbased design can provide the required design flexibility and speed by allowing the use of IP cores. However, testing costs in the SoC environment can reach a substantial percent of the total production cost. Analog testing costs may dominate the total test cost, as testing of analog circuits usually require functional verification of the circuit and special testing procedures. For RF analog circuits commonly used in wireless applications, testing is further complicated because of the high frequencies involved. In summary, reducing analog test cost is of major importance in the electronic industry today. BIST techniques for analog circuits, though potentially able to solve the analog test cost problem, have some limitations. Some techniques are circuit dependent, requiring reconfiguration of the circuit being tested, and are generally not usable in RF circuits. In the SoC environment, as processing and memory resources are available, they could be used in the test. However, the overhead for adding additional AD and DA converters may be too costly for most systems, and analog routing of signals may not be feasible and may introduce signal distortion. In this work a simple and low cost digitizer is used instead of an ADC in order to enable analog testing strategies to be implemented in a SoC environment. Thanks to the low analog area overhead of the converter...

Digital approach for the design of statistical analog data acquisition on SoCs

Souza Junior, Adao Antonio de
Fonte: Universidade Federal do Rio Grande do Sul Publicador: Universidade Federal do Rio Grande do Sul
Tipo: Tese de Doutorado Formato: application/pdf
ENG
Relevância na Pesquisa
36.7%
With the current demand for mixed-signal SoCs, an increasing number of designers are looking for ADC architectures that can be easily implemented over digital substrates. Since ADC performance is strongly dependent upon physical and electrical features, it gets more difficult for them to benefit from more recent technologies, where these features are more variable. This way, analog signal acquisition is not allowed to follow an evolutionary trend compatible with Moore’s Law. In fact, such trend shall get worst, since newer technologies are expected to have more variable characteristics. Also, for a matter of economy of scale, many times a mixed-signal SoC presents a good amount of idle processing power. In such systems it is advantageous to employ more costly digital signal processing provided that it allows a reduction in the analog area demanded or the use of less expensive analog blocks, able to cope with process variations and uncertainty. Besides the technological concerns, other factors that impact the cost of the design also advise to transfer problems from the analog to the digital domain whenever possible: design automation and self-test requirements, for instance. Recent surveys indicate that the total cost in designer hours for the analog blocks of a mixed-signal system can be up to three times the cost of the digital ones. This manuscript explores the concept of bottom-up analog acquisition design...

Analysis, design and implementation of analog/RF blocks suitable for a multi-band analog interface for CMOS SOCs; Análise, projeto e implementação de blocos analógicos/RF aplicados a uma interface analógica multi-banda para sistemas-em-chip (SOCs) em CMOS

Cortes, Fernando da Rocha Paixao
Fonte: Universidade Federal do Rio Grande do Sul Publicador: Universidade Federal do Rio Grande do Sul
Tipo: Tese de Doutorado Formato: application/pdf
ENG
Relevância na Pesquisa
36.65%
O desenvolvimento de tecnologias de integração para circuitos integrados junto com a demanda de cada vez mais processamento digital de sinais, como em sistemas de telecomunicações e aplicações SOC, resultaram na crescente necessidade de circuitos mistos em tecnologia CMOS integrados em um único chip. Em um trabalho anterior, a arquitetura de uma interface analógica para ser usada em aplicações SOC mistas foi desenvolvida e implementada. Basicamente esta interface é composta por uma célula analógica fixa (fixed analog cell – FAC), que translada o sinal de entrada para uma freqüência de processamento fixa, e por um bloco digital que processa este sinal. Primeiramente, as especificações de sistema foram determinadas considerando o processamento de sinais de três bandas de freqüência diferentes: FM, vídeo e celular, seguido por simulações de alto-nível do sistema da FAC. Então, uma arquitetura heteródina integrada CMOS para o front-end que integrará a FAC, composto por 2 mixers ativos e um amplificador de ganho variável, foi apresentada, enumerando-se e propondo-se soluções para os desafios de projeto e metodologia. Os blocos analógicos/RF, juntamente com o front-end, foram projetados e implementados em tecnologia CMOS IBM 0.18μm...

Proposta de implementação em hardware dedicado de redes neurais competitivas com técnicas de circuitos integrados analógicos; Proposal for implementation in dedicate hardware of competitive neural networks with analog integrated circuits techniques"

Molz, Rolf Fredi
Fonte: Universidade Federal do Rio Grande do Sul Publicador: Universidade Federal do Rio Grande do Sul
Tipo: Dissertação Formato: application/pdf
POR
Relevância na Pesquisa
36.56%
Neste trabalho apresenta-se uma proposta de uma técnica para implementação em hardware, das estruturas básicas de uma Rede Neural Competitiva, baseada em técnicas analógicas. Através desta proposta, será abordada uma das classes mais interessantes de Redes Neurais Artificiais (RNA) que são as Redes Neurais Competitivas (RNC), que possuem forte inspiração biológica. As equações fundamentais que descrevem o comportamento da RNC foram derivadas de estudos interdisciplinares, a maioria envolvendo observações neurofisiológicas. O estudo do neurônio biológico, por exemplo, nos leva a clássica equação da membrana. A técnica mostrada para a implementação das Redes Neurais Competitivas se baseia no use das técnicas analógicas. Estas conduzem a um projeto mais compacto além de permitirem um processamento em tempo real, visto que o circuito computacional analógico altera simultaneamente e continuamente todos os estados dos neurônios que se encontram interligados em paralelo. Para esta proposta de implementação, a mostrado que as equações fundamentais que governam as Redes Neurais Competitivas possuem uma relação com componentes eletrônicos básicos, podendo então, serem implementados através destes simples componentes com os quais as equações fundamentais se relacionam. Para tanto...

Analog reconfigurable technologies for EMG signal processing; Tecnologias analógicas reconfiguráveis para processamento de sinal eletromiográfico

Sanches, Paulo Roberto Stefani; Muller, Andre Frotta; Carro, Luigi; Susin, Altamiro Amadeu; Nohama, Percy
Fonte: Universidade Federal do Rio Grande do Sul Publicador: Universidade Federal do Rio Grande do Sul
Tipo: Artigo de Revista Científica Formato: application/pdf
ENG
Relevância na Pesquisa
36.61%
A aquisição e o processamento de sinais eletromiográficos é importante em aplicações clínicas envolvendo o diagnóstico de doenças, bem como no controle de próteses mioelétricas ou sistemas de estimulação elétrica funcional. Tradicionalmente os sinais eletromiográficos são processados usando-se circuitos analógicos, como amplificadores de instrumentação, filtros, conversores RMS ou de valor retificado médio. O projeto destes circuitos clássicos, embora bastante conhecidos, demanda tempo principalmente na fase de validação e testes. Neste artigo é mostrado o desenvolvimento de um circuito capaz de desempenhar essas funções empregando arranjos analógicos programáveis (Field Programmable Analog Arrays – FPAA). As funções mencionadas acima foram implementadas usando os recursos de um único arranjo analógico programável. A programação dos circuitos pode ser realizada a qualquer momento, através do “download” de uma nova configuração ou atualização da configuração atual durante a operação do sistema. O circuito com FPAA modelo AN221E04 do fabricante Anadigm mostrou excelente desempenho na captação de biopotenciais de amplitude baixa, da ordem de 10 μV a 500 μV e com interferências de modo comum significativamente superiores. O circuito mostrou-se versátil com a possibilidade de modificar as características dos circuitos analógicos...

Conversor digital quaternario para analogico; Quaternary digital to analog converter

Jose Carlos da Silva
Fonte: Biblioteca Digital da Unicamp Publicador: Biblioteca Digital da Unicamp
Tipo: Tese de Doutorado Formato: application/pdf
Publicado em 28/02/2005 PT
Relevância na Pesquisa
36.56%
Neste trabalho é apresentada a lógica múltiplo valor como opção para substituir ou ser usada como interface com a lógica binária. A lógica múltiplo valor difere da lógica binária clássica devido ao fato que os seus dígitos estão além de zeros e uns. Utilizando a lógica múltiplo valor consegue-se comunicação em entre blocos ou com o mundo externo a um chip com menor número de interconexões, o que acarretará a diminuição da área do circuito integrado e redução de custos. Pesquisadores e industria caminham para a pesquisa e desenvolvimento de circuitos múltiplos valores, que podem substituir ou ser utilizados como interface com os circuitos de dois valores (binários). Este trabalh o apresenta o desenvolvido do projeto de um conversor digital quaternário para analógico que tem quatro entradas e resolução equivalente a um conversor digital binário para analógico de oito entradas. Este conversor foi confeccionado totalmente em tecnologia CMOS 0.35µm, tendo como resultado um protótipo de um circuito integrado múltiplo valor que contém todas as células de um conversor digital binário para analógico. Este conversor apresenta consumo de potência abaixo de 1mW, alimentação simples de 5V e compactação (900µm x 235µm); In this work is presented the multiple value logic as option to substitute or to be used as interface with the binary logic. The multiple value logic differs of the classic binary logic to the fact that its digits are beyond zeros and ones. Using the multiple logic value obtains communication in between blocks or with the external world to one chip with lesser number of interconnections...

Sistema integrado para caracterização automática de conversores analógico-digitais; Integrated system for automated characterization of analog-digital converters

José Erick de Souza Lima
Fonte: Biblioteca Digital da Unicamp Publicador: Biblioteca Digital da Unicamp
Tipo: Dissertação de Mestrado Formato: application/pdf
Publicado em 31/05/2010 PT
Relevância na Pesquisa
36.61%
Este trabalho descreve um sistema constituído de diversos instrumentos, que se encontram interligados e gerenciados por um aplicativo de software, implementando um ambiente compacto para a caracterização de conversores analógico-digitais, de acordo com os procedimentos descritos nas normas IEEE 1057-1994 e IEEE 1241-2000. O sistema desenvolvido possui limitações quanto aos tipos de conversores analógico-digitais que podem ser testados, devidas às restrições impostas pelos equipamentos disponíveis neste momento. Sua estrutura, no entanto, foi concebida para permitir a expansão destes limites com a troca dos instrumentos limitantes à medida que estes forem adquiridos. A avaliação da sua funcionalidade foi realizada testando dois conversores analógico-digitais que têm características distintas. Enquanto um dos dispositivos testados tem resolução nominal de 10 bits e taxa de conversão de 80 MSPS, o outro tem resolução de 8 bits e taxa de conversão nominal de 8kSPS. A motivação para o desenvolvimento deste sistema está no projeto de conversores analógico-digitais integrados que se encontra em andamento no LPM-FEEC-Unicamp. A disponibilidade de um ambiente de teste com as propriedades do sistema desenvolvido é um requisito importante para o sucesso do projeto...

Analog "Neuronal" Networks in Early Vision

Koch, Christof; Marroquin, Jose; Yuille, Alan
Fonte: MIT - Massachusetts Institute of Technology Publicador: MIT - Massachusetts Institute of Technology
Formato: 17 p.; 3271888 bytes; 2548959 bytes; application/postscript; application/pdf
EN_US
Relevância na Pesquisa
36.56%
Many problems in early vision can be formulated in terms of minimizing an energy or cost function. Examples are shape-from-shading, edge detection, motion analysis, structure from motion and surface interpolation (Poggio, Torre and Koch, 1985). It has been shown that all quadratic variational problems, an important subset of early vision tasks, can be "solved" by linear, analog electrical or chemical networks (Poggio and Koch, 1985). IN a variety of situateions the cost function is non-quadratic, however, for instance in the presence of discontinuities. The use of non-quadratic cost functions raises the question of designing efficient algorithms for computing the optimal solution. Recently, Hopfield and Tank (1985) have shown that networks of nonlinear analog "neurons" can be effective in computing the solution of optimization problems. In this paper, we show how these networks can be generalized to solve the non-convex energy functionals of early vision. We illustrate this approach by implementing a specific network solving the problem of reconstructing a smooth surface while preserving its discontinuities from sparsely sampled data (Geman and Geman, 1984; Marroquin 1984; Terzopoulos 1984). These results suggest a novel computational strategy for solving such problems for both biological and artificial vision systems.

6.101 Introductory Analog Electronics Laboratory, Fall 2002; Introductory Analog Electronics Laboratory

Roscoe, Byron M.
Fonte: MIT - Massachusetts Institute of Technology Publicador: MIT - Massachusetts Institute of Technology
EN-US
Relevância na Pesquisa
36.65%
Introductory experimental laboratory explores the design, construction, and debugging of analog electronic circuits. Lectures and six laboratory projects investigate the performance characteristics of diodes, transistors, JFETs and op-amps, including the construction of a small audio amplifier and preamplifier. Seven weeks are devoted to the design and implementation of a project in an environment similar to that of engineering design teams in industry. Provides opportunity to simulate real-world problems and solutions that involve tradeoffs and the use of engineering judgement. From the course home page: Course Description 6.101 is an introductory electronics laboratory. Students learn about the basic principles of analog circuit design and operation in a practical, real-world laboratory setting. They work both with discrete components such as resistors, capacitors, diodes, and transistors as well as with integrated components such as operational amplifiers. In addition, they become familiar with the operation of basic electronic test equipment (digital multimeters, oscilloscopes, function generators, curve tracers, etc.). There are six labs due weekly which start out as cookbook types and progress to design exercises; there are group design projects for the second half of the term.

CMOS analog and radio-frequency integrated-circuit design employing low-power switched-capacitor techniques; Complementary-metal-oxide-semiconductor analog and radio-frequency integrated-circuit design employing low-power switched-capacitor techniques

Song, Yu (1980 - ); Ignjatovic, Zeljko
Fonte: University of Rochester Publicador: University of Rochester
Tipo: Tese de Doutorado Formato: Number of Pages:xviii, 177 leaves; Illustrations:ill. (some col.)
ENG
Relevância na Pesquisa
36.61%
Thesis (Ph. D.)--University of Rochester. Dept. of Electrical and Computer Engineering, 2011.; We propose and verify the design of low-power, high-performance CMOS Switched-Capacitor (SC) circuits for analog and radio-frequency (RF) applications. In low-cost CMOS semiconductor processes, SC circuits play a crucial role in implementing accurate analog signal processing functions. However, conventional SC circuits are usually power-demanding due to the accurate signal settling requirement. On the other hand, the shrinking of amplifier gain and voltage swing driven by technology scaling makes SC circuit design in deep sub-micron CMOS processes more and more challenging. To counteract these problems, low-power SC circuit techniques suitable for deep sub-micron CMOS processes are investigated in this work. In the first illustrative circuit example, a 2.5 GHz Phase-Locked-Loop (PLL) employing a new low-power SC loop filter is proposed, designed and verified in a 180nm CMOS technology. By employing the proposed SC loop filter, the advantages of low reference spur and small on-chip capacitor size are achieved. While the loop filter consumes a very low power, 1/f noise introduced by the inverter amplifier is also suppressed. The second circuit example is an audio-band highly-linear low-power multi-bit Delta-Sigma modulator with a SC nonlinearity-suppressed feedback DAC verified in a 130nm CMOS technology. By employing this proposed scheme...

Performance of photonic oversampled analog-to-digital converters.

Clare, Bradley
Fonte: Universidade de Adelaide Publicador: Universidade de Adelaide
Tipo: Tese de Doutorado Formato: 142171 bytes; 2066788 bytes; 2062883 bytes; 288700 bytes; application/pdf; application/pdf; application/pdf; application/pdf
Publicado em //2007 EN
Relevância na Pesquisa
36.65%
In an increasingly digital world, the need for high speed and high fidelity analog-to-digital (A/D) converters is paramount. Performance improvements in electronic A/Ds have not kept pace with demand, hence the need to consider alternative technologies. One such technology is photonics, as it takes advantage of optical sampling, high speed optical switches and low cross-talk interconnects. Optical sampling derives its advantage from the application of ultra low timing jitter (<100fs) mode locked lasers utilised to provide high speed clock pulses. In this thesis the feasibility and simulated performance of three different types of photonic oversampled A/D converters was investigated. The first, and simplest design is that of oversampled pulse-code-modulation (PCM), where a 2-level photonic comparator is used to sample the analog input at a frequency much greater than the Nyquist frequency. Subsequent low pass filtering produces a digital representation of the input. The other two architectures that were investigated are the first-order sigma-delta and error diffusion, which add one level of error correction to the PCM technique. These two architectures require the functional elements of a subtractor, comparator and delay. The photonic comparator and subtractor functionality was provided by Self-Electro-Optic Effect devices (SEED) based upon multiple quantum well (MQW) p-i-n devices. To facilitate calculation of the performance of the different architectures and aid in device design...

Design techniques for low power mixed analog-digital circuits with application to smart wireless systems.

Al-Sarawi, Said Fares Khalil
Fonte: Universidade de Adelaide Publicador: Universidade de Adelaide
Tipo: Tese de Doutorado
Publicado em //2003
Relevância na Pesquisa
36.65%
This dissertation presents and discusses new design techniques for mixed analog-digital circuits with emphases on low power and small area for standard low-cost CMOS VLSI technology. The application domain of the devised techniques is radio frequency identification (RFID) systems, however the presented techniques are applicable to wide range of mixed mode analog-digital applications. Hence the techniques herein apply to a range of smart wireless or mobile systems. The integration of both analog and digital circuits on a single substrate has many benefits such as reducing the system power, increasing the system reliability, reducing the system size and providing high inter-system communications speed - hence, a cost effective system implementation with increased performance. On the other hand, some difficulties arise from the fact that standard low-cost CMOS technologies are tuned toward maximising digital circuit performance and increasing transistor density per unit area. Usually these technologies have a wide spread in transistor parameters that require new design techniques that provide circuit characteristics based on relative transistor parameters rather than on the absolute value of these parameters. This research has identified new design techniques for mostly analog and some digital circuits for implementation in standard CMOS technologies with design parameters dependent on the relative values of process parameters...

Quantitative analysis of carbonate sandbodies : outcrop analog study from an epicontinental basin (Triassic Germany); Quantitative Analysis Of Carbonate Sandbodies: Outcrop Analog Study From An Epicontinental Basin (Triassic Germany)

Braun, Sascha
Fonte: Universidade de Tubinga Publicador: Universidade de Tubinga
Tipo: Dissertação
EN
Relevância na Pesquisa
36.7%
Scope This outcrop analog study aims to provide quantitative data concerning dimensions, spatial distribution, internal structure and poro-perm characteristics of carbonate shoal bodies on a carbonate ramp system. Shelly-oolitic carbonate bodies of the SW-German Upper Muschelkalk represent excellent outcrop analogs for hydrocarbon reservoirs in epeiric carbonate systems of the Middle East (e.g. Khuff, Hanifa, Arab). Methods & data Sampling of a few thousand polished slabs and detailed sedimentological logging in 21 outcrops plus outcrop gamma-ray measurements constitute the data basis for facies & genetic stratigraphic analysis. The reservoir quality of carbonate shoal bodies was quantified by more than 650 poro-perm samples. Thin section investigations analyzed diagenetic effects on phi / k using cathodoluminescence microscopy. Regional high resolution sequence stratigraphic correlations highlight the architecture and geometry of carbonate shoals while facies- and poro-perm maps show the continuity, distribution and potential of reservoir bodies. Results (* = Average values) • The best reservoir quality occurs in (1) shell hash grainstones (phi* = 15 %, k* = 45 mD) and (2) poorly sorted, bioclastic grainstones (phi* = 13 %, k* = 82 mD) on wind-sheltered leeward sides of the shoals...

Analog-to-digital signal processing in a prototype SATCOM signal analyzer

Ohlson, John Everett; Zell, William B.
Fonte: Monterey, California. Naval Postgraduate School Publicador: Monterey, California. Naval Postgraduate School
Tipo: Relatório Formato: 103 p. : ill. ; 28 cm.
EN_US
Relevância na Pesquisa
36.61%
A prototype SATCOM Signal Analyzer (SSA) has been designed which performs spectral analysis on transponder signals from the Navy's UHF communications satellites. As an integral part of the SSA, the Analog to Digital Control and Conversion subsystem converts four channels of baseband analog signals into equivalent digital representations while operating at variable sampling rates and offering either twelve or eight bits of resolution of the analog signal. The digital data thus derived is presented to an array processor for Fast Fourier Transform processing. This report documents the design and construction of the Analog to Digital Control and Conversion subsystem.; Prepared for: Naval Electronic Systems Command PME-106-1, Washington, D.C. 20360 -- Cover.; http://archive.org/details/analogtodigitals00ohls; N0003980WR09137; NA

Analog integrated circuit design in ultra-thin oxide CMOS technologies with significant direct tunneling-induced gate current

Bohannon, Eric
Fonte: Rochester Instituto de Tecnologia Publicador: Rochester Instituto de Tecnologia
Tipo: Dissertação
EN_US
Relevância na Pesquisa
36.61%
The ability to do mixed-signal IC design in a CMOS technology has been a driving force for manufacturing personal mobile electronic products such as cellular phones, digital audio players, and personal digital assistants. As CMOS has moved to ultra-thin oxide technologies, where oxide thicknesses are less than 3 nm, this type of design has been threatened by the direct tunneling of carriers though the gate oxide. This type of tunneling, which increases exponentially with decreasing oxide thickness, is a source of MOSFET gate current. Its existence invalidates the simplifying design assumption of infinite gate resistance. Its problems are typically avoided by switching to a high-&kappa/metal gate technology or by including a second thick(er) oxide transistor. Both of these solutions come with undesirable increases in cost due to extra mask and processing steps. Furthermore, digital circuit solutions to the problems created by direct tunneling are available, while analog circuit solutions are not. Therefore, it is desirable that analog circuit solutions exist that allow the design of mixed-signal circuits with ultra-thin oxide MOSFETs. This work presents a methodology that develops these solutions as a less costly alternative to high-&kappa/metal gate technologies or thick(er) oxide transistors. The solutions focus on transistor sizing...

Analog joint source-channel coding for non-standard scenarios

Lu, Bo
Fonte: University of Delaware Publicador: University of Delaware
Tipo: Tese de Doutorado
Relevância na Pesquisa
36.65%
Garcia-Frias, Javier; Recently, analog joint source-channel coding (JSCC) systems based on mappings have become one of the most promising schemes for transmitting discrete-time, continuous-amplitude sources (e.g., audio and video samples) over time-varying channels (e.g., wireless channels) under complexity and delay constraints. In contrast to traditional digital communication systems based on Shannon's separation principle, analog JSCC schemes are robust to changes in the channel quality, and do not require near infinite block lengths to approach the theoretical limits. As a result, the encoding/decoding complexity and delay can be greatly reduced compared with digital schemes. Direct source-channel mappings take K discrete-time, continuous-amplitude symbols (a K dimensional vector in the source space) and map them directly into L discrete-time, continuous-amplitude channel symbols (an L dimensional vector in the channel space), achieving either bandwidth reduction (K > L ) or bandwidth expansion (K Direct source-channel mappings take K discrete-time, continuous-amplitude symbols (a K dimensional vector in the source space) and map them directly into L discrete-time, continuous-amplitude channel symbols (an L dimensional vector in the channel space)...

A Robust Evolvable System for the Synthesis of Analog Circuits

Torres Soto,Aurora; Ponce de León Sentí,Eunice E.; Hernández Aguirre,Arturo; Torres Soto,María Dolores; Díaz Díaz,Elva
Fonte: Centro de Investigación en computación, IPN Publicador: Centro de Investigación en computación, IPN
Tipo: Artigo de Revista Científica Formato: text/html
Publicado em 01/06/2010 EN
Relevância na Pesquisa
36.65%
This paper presents a group of evolutionary mechanisms for the design of analog circuits, embedded on a genetic algorithm that performs the synthesis of an analog filter. The algorithm interacts with SPICE, to evaluate the fitness of evolved circuits. In order to model an analog circuit, a linear representation is introduced and its corresponding reproduction operators that preserve the valid topological analog circuit class closed. The novelty of this paper consists of the use of a linear representation in combination with the generation mechanism and closed operators that keep the non SPICE simulable circuits below one percent. Furthermore, the concept of preferred values is used into the generation mechanism and genetic operators in order to reduce the gap between the real circuits and the evolvable ones. The performance of the system at designing passive low pass filter is discussed and experiments performed show its efficiency.